1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -march=x86 | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker 3*9880d681SAndroid Build Coastguard Worker; This test should get one and only one register to register mov. 4*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: t: 5*9880d681SAndroid Build Coastguard Worker; CHECK: movl 6*9880d681SAndroid Build Coastguard Worker; CHECK-NOT: mov 7*9880d681SAndroid Build Coastguard Worker; CHECK: ret 8*9880d681SAndroid Build Coastguard Worker 9*9880d681SAndroid Build Coastguard Workerdefine signext i16 @t() { 10*9880d681SAndroid Build Coastguard Workerentry: 11*9880d681SAndroid Build Coastguard Worker %tmp180 = load i16, i16* null, align 2 ; <i16> [#uses=3] 12*9880d681SAndroid Build Coastguard Worker %tmp180181 = sext i16 %tmp180 to i32 ; <i32> [#uses=1] 13*9880d681SAndroid Build Coastguard Worker %tmp182 = add i16 %tmp180, 10 14*9880d681SAndroid Build Coastguard Worker %tmp185 = icmp slt i16 %tmp182, 0 ; <i1> [#uses=1] 15*9880d681SAndroid Build Coastguard Worker br i1 %tmp185, label %cond_true188, label %cond_next245 16*9880d681SAndroid Build Coastguard Worker 17*9880d681SAndroid Build Coastguard Workercond_true188: ; preds = %entry 18*9880d681SAndroid Build Coastguard Worker %tmp195196 = trunc i16 %tmp180 to i8 ; <i8> [#uses=0] 19*9880d681SAndroid Build Coastguard Worker ret i16 %tmp180 20*9880d681SAndroid Build Coastguard Worker 21*9880d681SAndroid Build Coastguard Workercond_next245: ; preds = %entry 22*9880d681SAndroid Build Coastguard Worker %tmp256 = and i32 %tmp180181, 15 ; <i32> [#uses=0] 23*9880d681SAndroid Build Coastguard Worker %tmp3 = trunc i32 %tmp256 to i16 24*9880d681SAndroid Build Coastguard Worker ret i16 %tmp3 25*9880d681SAndroid Build Coastguard Worker} 26