1*9880d681SAndroid Build Coastguard Worker; RUN: llc -march=x86 -mcpu=i486 -o - %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker 3*9880d681SAndroid Build Coastguard Worker; Main test here was that ISelDAG could cope with a MachineNode in the chain 4*9880d681SAndroid Build Coastguard Worker; from the first load to the "X86ISD::SUB". Previously it thought that meant no 5*9880d681SAndroid Build Coastguard Worker; cycle could be formed so it tried to use "sub (%eax), [[RHS]]". 6*9880d681SAndroid Build Coastguard Worker 7*9880d681SAndroid Build Coastguard Workerdefine void @gst_atomic_queue_push(i32* %addr) { 8*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: gst_atomic_queue_push: 9*9880d681SAndroid Build Coastguard Worker; CHECK: movl (%eax), [[LHS:%e[a-z]+]] 10*9880d681SAndroid Build Coastguard Worker; CHECK: lock orl 11*9880d681SAndroid Build Coastguard Worker; CHECK: movl (%eax), [[RHS:%e[a-z]+]] 12*9880d681SAndroid Build Coastguard Worker; CHECK: cmpl [[LHS]], [[RHS]] 13*9880d681SAndroid Build Coastguard Worker 14*9880d681SAndroid Build Coastguard Workerentry: 15*9880d681SAndroid Build Coastguard Worker br label %while.body 16*9880d681SAndroid Build Coastguard Worker 17*9880d681SAndroid Build Coastguard Workerwhile.body: 18*9880d681SAndroid Build Coastguard Worker %0 = load volatile i32, i32* %addr, align 4 19*9880d681SAndroid Build Coastguard Worker fence seq_cst 20*9880d681SAndroid Build Coastguard Worker %1 = load volatile i32, i32* %addr, align 4 21*9880d681SAndroid Build Coastguard Worker %cmp = icmp sgt i32 %1, %0 22*9880d681SAndroid Build Coastguard Worker br i1 %cmp, label %while.body, label %if.then 23*9880d681SAndroid Build Coastguard Worker 24*9880d681SAndroid Build Coastguard Workerif.then: 25*9880d681SAndroid Build Coastguard Worker ret void 26*9880d681SAndroid Build Coastguard Worker}