1*9880d681SAndroid Build Coastguard Worker; RUN: llc -mcpu=yonah < %s 2*9880d681SAndroid Build Coastguard Worker; PR9438 3*9880d681SAndroid Build Coastguard Workertarget datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" 4*9880d681SAndroid Build Coastguard Workertarget triple = "i386-unknown-freebsd9.0" 5*9880d681SAndroid Build Coastguard Worker 6*9880d681SAndroid Build Coastguard Worker; The 'call fastcc' ties down %ebx, %ecx, and %edx. 7*9880d681SAndroid Build Coastguard Worker; A MUL8r ties down %al, leaving no GR32_ABCD registers available. 8*9880d681SAndroid Build Coastguard Worker; The coalescer can easily overallocate physical registers, 9*9880d681SAndroid Build Coastguard Worker; and register allocation fails. 10*9880d681SAndroid Build Coastguard Worker 11*9880d681SAndroid Build Coastguard Workerdeclare fastcc i8* @save_string(i8* %d, i8* nocapture %s) nounwind 12*9880d681SAndroid Build Coastguard Worker 13*9880d681SAndroid Build Coastguard Workerdefine i32 @cvtchar(i8* nocapture %sp) nounwind { 14*9880d681SAndroid Build Coastguard Worker %temp.i = alloca [2 x i8], align 1 15*9880d681SAndroid Build Coastguard Worker %tmp1 = load i8, i8* %sp, align 1 16*9880d681SAndroid Build Coastguard Worker %div = udiv i8 %tmp1, 10 17*9880d681SAndroid Build Coastguard Worker %rem = urem i8 %div, 10 18*9880d681SAndroid Build Coastguard Worker %arrayidx.i = getelementptr inbounds [2 x i8], [2 x i8]* %temp.i, i32 0, i32 0 19*9880d681SAndroid Build Coastguard Worker store i8 %rem, i8* %arrayidx.i, align 1 20*9880d681SAndroid Build Coastguard Worker %call.i = call fastcc i8* @save_string(i8* %sp, i8* %arrayidx.i) nounwind 21*9880d681SAndroid Build Coastguard Worker ret i32 undef 22*9880d681SAndroid Build Coastguard Worker} 23