1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s 2*9880d681SAndroid Build Coastguard Worker; PR6374 3*9880d681SAndroid Build Coastguard Worker; 4*9880d681SAndroid Build Coastguard Worker; This test produces a DIV8r instruction and uses %AX instead of %AH and %AL. 5*9880d681SAndroid Build Coastguard Worker; The DIV8r must have the right imp-defs for that to work. 6*9880d681SAndroid Build Coastguard Workertarget datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" 7*9880d681SAndroid Build Coastguard Workertarget triple = "x86_64-apple-darwin10.0.0" 8*9880d681SAndroid Build Coastguard Worker 9*9880d681SAndroid Build Coastguard Worker%struct._i386_state = type { %union.anon } 10*9880d681SAndroid Build Coastguard Worker%union.anon = type { [0 x i8] } 11*9880d681SAndroid Build Coastguard Worker 12*9880d681SAndroid Build Coastguard Workerdefine void @i386_aam(%struct._i386_state* nocapture %cpustate) nounwind ssp { 13*9880d681SAndroid Build Coastguard Workerentry: 14*9880d681SAndroid Build Coastguard Worker %call = tail call fastcc signext i8 @FETCH() ; <i8> [#uses=1] 15*9880d681SAndroid Build Coastguard Worker %rem = urem i8 0, %call ; <i8> [#uses=1] 16*9880d681SAndroid Build Coastguard Worker store i8 %rem, i8* undef 17*9880d681SAndroid Build Coastguard Worker ret void 18*9880d681SAndroid Build Coastguard Worker} 19*9880d681SAndroid Build Coastguard Worker 20*9880d681SAndroid Build Coastguard Workerdeclare fastcc signext i8 @FETCH() nounwind readnone ssp 21