1*9880d681SAndroid Build Coastguard Worker; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=cortex-m0 < %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.) 3*9880d681SAndroid Build Coastguard Worker; rdar://11331541 4*9880d681SAndroid Build Coastguard Worker 5*9880d681SAndroid Build Coastguard Workerdefine i32 @t(i32 %a) nounwind { 6*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: t: 7*9880d681SAndroid Build Coastguard Worker; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31 8*9880d681SAndroid Build Coastguard Worker; CHECK: eors [[REG2]], [[REG1]] 9*9880d681SAndroid Build Coastguard Worker %tmp0 = ashr i32 %a, 31 10*9880d681SAndroid Build Coastguard Worker %tmp1 = xor i32 %tmp0, %a 11*9880d681SAndroid Build Coastguard Worker ret i32 %tmp1 12*9880d681SAndroid Build Coastguard Worker} 13