1*9880d681SAndroid Build Coastguard Worker; Test high-word operations, using "h" constraints to force a high 2*9880d681SAndroid Build Coastguard Worker; register and "r" constraints to force a low register. 3*9880d681SAndroid Build Coastguard Worker; 4*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z196 \ 5*9880d681SAndroid Build Coastguard Worker; RUN: -no-integrated-as | FileCheck %s 6*9880d681SAndroid Build Coastguard Worker 7*9880d681SAndroid Build Coastguard Worker; Test loads and stores involving mixtures of high and low registers. 8*9880d681SAndroid Build Coastguard Workerdefine void @f1(i32 *%ptr1, i32 *%ptr2) { 9*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f1: 10*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lfh [[REG1:%r[0-5]]], 0(%r2) 11*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: l [[REG2:%r[0-5]]], 0(%r3) 12*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lfh [[REG3:%r[0-5]]], 4096(%r2) 13*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: ly [[REG4:%r[0-5]]], 524284(%r3) 14*9880d681SAndroid Build Coastguard Worker; CHECK: blah [[REG1]], [[REG2]], [[REG3]], [[REG4]] 15*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: stfh [[REG1]], 0(%r2) 16*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: st [[REG2]], 0(%r3) 17*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: stfh [[REG3]], 4096(%r2) 18*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: sty [[REG4]], 524284(%r3) 19*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 20*9880d681SAndroid Build Coastguard Worker %ptr3 = getelementptr i32, i32 *%ptr1, i64 1024 21*9880d681SAndroid Build Coastguard Worker %ptr4 = getelementptr i32, i32 *%ptr2, i64 131071 22*9880d681SAndroid Build Coastguard Worker %old1 = load i32 , i32 *%ptr1 23*9880d681SAndroid Build Coastguard Worker %old2 = load i32 , i32 *%ptr2 24*9880d681SAndroid Build Coastguard Worker %old3 = load i32 , i32 *%ptr3 25*9880d681SAndroid Build Coastguard Worker %old4 = load i32 , i32 *%ptr4 26*9880d681SAndroid Build Coastguard Worker %res = call { i32, i32, i32, i32 } asm "blah $0, $1, $2, $3", 27*9880d681SAndroid Build Coastguard Worker "=h,=r,=h,=r,0,1,2,3"(i32 %old1, i32 %old2, i32 %old3, i32 %old4) 28*9880d681SAndroid Build Coastguard Worker %new1 = extractvalue { i32, i32, i32, i32 } %res, 0 29*9880d681SAndroid Build Coastguard Worker %new2 = extractvalue { i32, i32, i32, i32 } %res, 1 30*9880d681SAndroid Build Coastguard Worker %new3 = extractvalue { i32, i32, i32, i32 } %res, 2 31*9880d681SAndroid Build Coastguard Worker %new4 = extractvalue { i32, i32, i32, i32 } %res, 3 32*9880d681SAndroid Build Coastguard Worker store i32 %new1, i32 *%ptr1 33*9880d681SAndroid Build Coastguard Worker store i32 %new2, i32 *%ptr2 34*9880d681SAndroid Build Coastguard Worker store i32 %new3, i32 *%ptr3 35*9880d681SAndroid Build Coastguard Worker store i32 %new4, i32 *%ptr4 36*9880d681SAndroid Build Coastguard Worker ret void 37*9880d681SAndroid Build Coastguard Worker} 38*9880d681SAndroid Build Coastguard Worker 39*9880d681SAndroid Build Coastguard Worker; Test moves involving mixtures of high and low registers. 40*9880d681SAndroid Build Coastguard Workerdefine i32 @f2(i32 %old) { 41*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f2: 42*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: risbhg [[REG1:%r[0-5]]], %r2, 0, 159, 32 43*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lr %r3, %r2 44*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG1]], %r2, %r3 45*9880d681SAndroid Build Coastguard Worker; CHECK: risbhg {{%r[0-5]}}, [[REG1]], 0, 159, 0 46*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG2:%r[0-5]]] 47*9880d681SAndroid Build Coastguard Worker; CHECK: risblg %r2, [[REG2]], 0, 159, 32 48*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 49*9880d681SAndroid Build Coastguard Worker %tmp = call i32 asm "stepa $1, $2, $3", 50*9880d681SAndroid Build Coastguard Worker "=h,0,{r2},{r3}"(i32 %old, i32 %old, i32 %old) 51*9880d681SAndroid Build Coastguard Worker %new = call i32 asm "stepb $1, $2", "=&h,0,h"(i32 %tmp, i32 %tmp) 52*9880d681SAndroid Build Coastguard Worker ret i32 %new 53*9880d681SAndroid Build Coastguard Worker} 54*9880d681SAndroid Build Coastguard Worker 55*9880d681SAndroid Build Coastguard Worker; Test sign-extending 8-bit loads into mixtures of high and low registers. 56*9880d681SAndroid Build Coastguard Workerdefine void @f3(i8 *%ptr1, i8 *%ptr2) { 57*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f3: 58*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lbh [[REG1:%r[0-5]]], 0(%r2) 59*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lb [[REG2:%r[0-5]]], 0(%r3) 60*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lbh [[REG3:%r[0-5]]], 4096(%r2) 61*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lb [[REG4:%r[0-5]]], 524287(%r3) 62*9880d681SAndroid Build Coastguard Worker; CHECK: blah [[REG1]], [[REG2]] 63*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 64*9880d681SAndroid Build Coastguard Worker %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096 65*9880d681SAndroid Build Coastguard Worker %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287 66*9880d681SAndroid Build Coastguard Worker %val1 = load i8 , i8 *%ptr1 67*9880d681SAndroid Build Coastguard Worker %val2 = load i8 , i8 *%ptr2 68*9880d681SAndroid Build Coastguard Worker %val3 = load i8 , i8 *%ptr3 69*9880d681SAndroid Build Coastguard Worker %val4 = load i8 , i8 *%ptr4 70*9880d681SAndroid Build Coastguard Worker %ext1 = sext i8 %val1 to i32 71*9880d681SAndroid Build Coastguard Worker %ext2 = sext i8 %val2 to i32 72*9880d681SAndroid Build Coastguard Worker %ext3 = sext i8 %val3 to i32 73*9880d681SAndroid Build Coastguard Worker %ext4 = sext i8 %val4 to i32 74*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "blah $0, $1, $2, $3", 75*9880d681SAndroid Build Coastguard Worker "h,r,h,r"(i32 %ext1, i32 %ext2, i32 %ext3, i32 %ext4) 76*9880d681SAndroid Build Coastguard Worker ret void 77*9880d681SAndroid Build Coastguard Worker} 78*9880d681SAndroid Build Coastguard Worker 79*9880d681SAndroid Build Coastguard Worker; Test sign-extending 16-bit loads into mixtures of high and low registers. 80*9880d681SAndroid Build Coastguard Workerdefine void @f4(i16 *%ptr1, i16 *%ptr2) { 81*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f4: 82*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lhh [[REG1:%r[0-5]]], 0(%r2) 83*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lh [[REG2:%r[0-5]]], 0(%r3) 84*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lhh [[REG3:%r[0-5]]], 4096(%r2) 85*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lhy [[REG4:%r[0-5]]], 524286(%r3) 86*9880d681SAndroid Build Coastguard Worker; CHECK: blah [[REG1]], [[REG2]] 87*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 88*9880d681SAndroid Build Coastguard Worker %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048 89*9880d681SAndroid Build Coastguard Worker %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143 90*9880d681SAndroid Build Coastguard Worker %val1 = load i16 , i16 *%ptr1 91*9880d681SAndroid Build Coastguard Worker %val2 = load i16 , i16 *%ptr2 92*9880d681SAndroid Build Coastguard Worker %val3 = load i16 , i16 *%ptr3 93*9880d681SAndroid Build Coastguard Worker %val4 = load i16 , i16 *%ptr4 94*9880d681SAndroid Build Coastguard Worker %ext1 = sext i16 %val1 to i32 95*9880d681SAndroid Build Coastguard Worker %ext2 = sext i16 %val2 to i32 96*9880d681SAndroid Build Coastguard Worker %ext3 = sext i16 %val3 to i32 97*9880d681SAndroid Build Coastguard Worker %ext4 = sext i16 %val4 to i32 98*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "blah $0, $1, $2, $3", 99*9880d681SAndroid Build Coastguard Worker "h,r,h,r"(i32 %ext1, i32 %ext2, i32 %ext3, i32 %ext4) 100*9880d681SAndroid Build Coastguard Worker ret void 101*9880d681SAndroid Build Coastguard Worker} 102*9880d681SAndroid Build Coastguard Worker 103*9880d681SAndroid Build Coastguard Worker; Test zero-extending 8-bit loads into mixtures of high and low registers. 104*9880d681SAndroid Build Coastguard Workerdefine void @f5(i8 *%ptr1, i8 *%ptr2) { 105*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f5: 106*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llch [[REG1:%r[0-5]]], 0(%r2) 107*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llc [[REG2:%r[0-5]]], 0(%r3) 108*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llch [[REG3:%r[0-5]]], 4096(%r2) 109*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llc [[REG4:%r[0-5]]], 524287(%r3) 110*9880d681SAndroid Build Coastguard Worker; CHECK: blah [[REG1]], [[REG2]] 111*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 112*9880d681SAndroid Build Coastguard Worker %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096 113*9880d681SAndroid Build Coastguard Worker %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287 114*9880d681SAndroid Build Coastguard Worker %val1 = load i8 , i8 *%ptr1 115*9880d681SAndroid Build Coastguard Worker %val2 = load i8 , i8 *%ptr2 116*9880d681SAndroid Build Coastguard Worker %val3 = load i8 , i8 *%ptr3 117*9880d681SAndroid Build Coastguard Worker %val4 = load i8 , i8 *%ptr4 118*9880d681SAndroid Build Coastguard Worker %ext1 = zext i8 %val1 to i32 119*9880d681SAndroid Build Coastguard Worker %ext2 = zext i8 %val2 to i32 120*9880d681SAndroid Build Coastguard Worker %ext3 = zext i8 %val3 to i32 121*9880d681SAndroid Build Coastguard Worker %ext4 = zext i8 %val4 to i32 122*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "blah $0, $1, $2, $3", 123*9880d681SAndroid Build Coastguard Worker "h,r,h,r"(i32 %ext1, i32 %ext2, i32 %ext3, i32 %ext4) 124*9880d681SAndroid Build Coastguard Worker ret void 125*9880d681SAndroid Build Coastguard Worker} 126*9880d681SAndroid Build Coastguard Worker 127*9880d681SAndroid Build Coastguard Worker; Test zero-extending 16-bit loads into mixtures of high and low registers. 128*9880d681SAndroid Build Coastguard Workerdefine void @f6(i16 *%ptr1, i16 *%ptr2) { 129*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f6: 130*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llhh [[REG1:%r[0-5]]], 0(%r2) 131*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llh [[REG2:%r[0-5]]], 0(%r3) 132*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llhh [[REG3:%r[0-5]]], 4096(%r2) 133*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llh [[REG4:%r[0-5]]], 524286(%r3) 134*9880d681SAndroid Build Coastguard Worker; CHECK: blah [[REG1]], [[REG2]] 135*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 136*9880d681SAndroid Build Coastguard Worker %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048 137*9880d681SAndroid Build Coastguard Worker %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143 138*9880d681SAndroid Build Coastguard Worker %val1 = load i16 , i16 *%ptr1 139*9880d681SAndroid Build Coastguard Worker %val2 = load i16 , i16 *%ptr2 140*9880d681SAndroid Build Coastguard Worker %val3 = load i16 , i16 *%ptr3 141*9880d681SAndroid Build Coastguard Worker %val4 = load i16 , i16 *%ptr4 142*9880d681SAndroid Build Coastguard Worker %ext1 = zext i16 %val1 to i32 143*9880d681SAndroid Build Coastguard Worker %ext2 = zext i16 %val2 to i32 144*9880d681SAndroid Build Coastguard Worker %ext3 = zext i16 %val3 to i32 145*9880d681SAndroid Build Coastguard Worker %ext4 = zext i16 %val4 to i32 146*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "blah $0, $1, $2, $3", 147*9880d681SAndroid Build Coastguard Worker "h,r,h,r"(i32 %ext1, i32 %ext2, i32 %ext3, i32 %ext4) 148*9880d681SAndroid Build Coastguard Worker ret void 149*9880d681SAndroid Build Coastguard Worker} 150*9880d681SAndroid Build Coastguard Worker 151*9880d681SAndroid Build Coastguard Worker; Test truncating stores of high and low registers into 8-bit memory. 152*9880d681SAndroid Build Coastguard Workerdefine void @f7(i8 *%ptr1, i8 *%ptr2) { 153*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f7: 154*9880d681SAndroid Build Coastguard Worker; CHECK: blah [[REG1:%r[0-5]]], [[REG2:%r[0-5]]] 155*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: stch [[REG1]], 0(%r2) 156*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: stc [[REG2]], 0(%r3) 157*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: stch [[REG1]], 4096(%r2) 158*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: stcy [[REG2]], 524287(%r3) 159*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 160*9880d681SAndroid Build Coastguard Worker %res = call { i32, i32 } asm "blah $0, $1", "=h,=r"() 161*9880d681SAndroid Build Coastguard Worker %res1 = extractvalue { i32, i32 } %res, 0 162*9880d681SAndroid Build Coastguard Worker %res2 = extractvalue { i32, i32 } %res, 1 163*9880d681SAndroid Build Coastguard Worker %trunc1 = trunc i32 %res1 to i8 164*9880d681SAndroid Build Coastguard Worker %trunc2 = trunc i32 %res2 to i8 165*9880d681SAndroid Build Coastguard Worker %ptr3 = getelementptr i8, i8 *%ptr1, i64 4096 166*9880d681SAndroid Build Coastguard Worker %ptr4 = getelementptr i8, i8 *%ptr2, i64 524287 167*9880d681SAndroid Build Coastguard Worker store i8 %trunc1, i8 *%ptr1 168*9880d681SAndroid Build Coastguard Worker store i8 %trunc2, i8 *%ptr2 169*9880d681SAndroid Build Coastguard Worker store i8 %trunc1, i8 *%ptr3 170*9880d681SAndroid Build Coastguard Worker store i8 %trunc2, i8 *%ptr4 171*9880d681SAndroid Build Coastguard Worker ret void 172*9880d681SAndroid Build Coastguard Worker} 173*9880d681SAndroid Build Coastguard Worker 174*9880d681SAndroid Build Coastguard Worker; Test truncating stores of high and low registers into 16-bit memory. 175*9880d681SAndroid Build Coastguard Workerdefine void @f8(i16 *%ptr1, i16 *%ptr2) { 176*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f8: 177*9880d681SAndroid Build Coastguard Worker; CHECK: blah [[REG1:%r[0-5]]], [[REG2:%r[0-5]]] 178*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: sthh [[REG1]], 0(%r2) 179*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: sth [[REG2]], 0(%r3) 180*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: sthh [[REG1]], 4096(%r2) 181*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: sthy [[REG2]], 524286(%r3) 182*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 183*9880d681SAndroid Build Coastguard Worker %res = call { i32, i32 } asm "blah $0, $1", "=h,=r"() 184*9880d681SAndroid Build Coastguard Worker %res1 = extractvalue { i32, i32 } %res, 0 185*9880d681SAndroid Build Coastguard Worker %res2 = extractvalue { i32, i32 } %res, 1 186*9880d681SAndroid Build Coastguard Worker %trunc1 = trunc i32 %res1 to i16 187*9880d681SAndroid Build Coastguard Worker %trunc2 = trunc i32 %res2 to i16 188*9880d681SAndroid Build Coastguard Worker %ptr3 = getelementptr i16, i16 *%ptr1, i64 2048 189*9880d681SAndroid Build Coastguard Worker %ptr4 = getelementptr i16, i16 *%ptr2, i64 262143 190*9880d681SAndroid Build Coastguard Worker store i16 %trunc1, i16 *%ptr1 191*9880d681SAndroid Build Coastguard Worker store i16 %trunc2, i16 *%ptr2 192*9880d681SAndroid Build Coastguard Worker store i16 %trunc1, i16 *%ptr3 193*9880d681SAndroid Build Coastguard Worker store i16 %trunc2, i16 *%ptr4 194*9880d681SAndroid Build Coastguard Worker ret void 195*9880d681SAndroid Build Coastguard Worker} 196*9880d681SAndroid Build Coastguard Worker 197*9880d681SAndroid Build Coastguard Worker; Test zero extensions from 8 bits between mixtures of high and low registers. 198*9880d681SAndroid Build Coastguard Workerdefine i32 @f9(i8 %val1, i8 %val2) { 199*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f9: 200*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: risbhg [[REG1:%r[0-5]]], %r2, 24, 159, 32 201*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llcr [[REG2:%r[0-5]]], %r3 202*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG1]], [[REG2]] 203*9880d681SAndroid Build Coastguard Worker; CHECK: risbhg [[REG3:%r[0-5]]], [[REG1]], 24, 159, 0 204*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG3]] 205*9880d681SAndroid Build Coastguard Worker; CHECK: risblg %r2, [[REG3]], 24, 159, 32 206*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 207*9880d681SAndroid Build Coastguard Worker %ext1 = zext i8 %val1 to i32 208*9880d681SAndroid Build Coastguard Worker %ext2 = zext i8 %val2 to i32 209*9880d681SAndroid Build Coastguard Worker %val3 = call i8 asm sideeffect "stepa $0, $1", "=h,0,r"(i32 %ext1, i32 %ext2) 210*9880d681SAndroid Build Coastguard Worker %ext3 = zext i8 %val3 to i32 211*9880d681SAndroid Build Coastguard Worker %val4 = call i8 asm sideeffect "stepb $0", "=h,0"(i32 %ext3) 212*9880d681SAndroid Build Coastguard Worker %ext4 = zext i8 %val4 to i32 213*9880d681SAndroid Build Coastguard Worker ret i32 %ext4 214*9880d681SAndroid Build Coastguard Worker} 215*9880d681SAndroid Build Coastguard Worker 216*9880d681SAndroid Build Coastguard Worker; Test zero extensions from 16 bits between mixtures of high and low registers. 217*9880d681SAndroid Build Coastguard Workerdefine i32 @f10(i16 %val1, i16 %val2) { 218*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f10: 219*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: risbhg [[REG1:%r[0-5]]], %r2, 16, 159, 32 220*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llhr [[REG2:%r[0-5]]], %r3 221*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG1]], [[REG2]] 222*9880d681SAndroid Build Coastguard Worker; CHECK: risbhg [[REG3:%r[0-5]]], [[REG1]], 16, 159, 0 223*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG3]] 224*9880d681SAndroid Build Coastguard Worker; CHECK: risblg %r2, [[REG3]], 16, 159, 32 225*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 226*9880d681SAndroid Build Coastguard Worker %ext1 = zext i16 %val1 to i32 227*9880d681SAndroid Build Coastguard Worker %ext2 = zext i16 %val2 to i32 228*9880d681SAndroid Build Coastguard Worker %val3 = call i16 asm sideeffect "stepa $0, $1", "=h,0,r"(i32 %ext1, i32 %ext2) 229*9880d681SAndroid Build Coastguard Worker %ext3 = zext i16 %val3 to i32 230*9880d681SAndroid Build Coastguard Worker %val4 = call i16 asm sideeffect "stepb $0", "=h,0"(i32 %ext3) 231*9880d681SAndroid Build Coastguard Worker %ext4 = zext i16 %val4 to i32 232*9880d681SAndroid Build Coastguard Worker ret i32 %ext4 233*9880d681SAndroid Build Coastguard Worker} 234*9880d681SAndroid Build Coastguard Worker 235*9880d681SAndroid Build Coastguard Worker; Test loads of 16-bit constants into mixtures of high and low registers. 236*9880d681SAndroid Build Coastguard Workerdefine void @f11() { 237*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f11: 238*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: iihf [[REG1:%r[0-5]]], 4294934529 239*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lhi [[REG2:%r[0-5]]], -32768 240*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llihl [[REG3:%r[0-5]]], 32766 241*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: lhi [[REG4:%r[0-5]]], 32767 242*9880d681SAndroid Build Coastguard Worker; CHECK: blah [[REG1]], [[REG2]], [[REG3]], [[REG4]] 243*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 244*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "blah $0, $1, $2, $3", 245*9880d681SAndroid Build Coastguard Worker "h,r,h,r"(i32 -32767, i32 -32768, 246*9880d681SAndroid Build Coastguard Worker i32 32766, i32 32767) 247*9880d681SAndroid Build Coastguard Worker ret void 248*9880d681SAndroid Build Coastguard Worker} 249*9880d681SAndroid Build Coastguard Worker 250*9880d681SAndroid Build Coastguard Worker; Test loads of unsigned constants into mixtures of high and low registers. 251*9880d681SAndroid Build Coastguard Worker; For stepc, we expect the h and r operands to be paired by the register 252*9880d681SAndroid Build Coastguard Worker; allocator. It doesn't really matter which comes first: LLILL/IIHF would 253*9880d681SAndroid Build Coastguard Worker; be just as good. 254*9880d681SAndroid Build Coastguard Workerdefine void @f12() { 255*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f12: 256*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llihl [[REG1:%r[0-5]]], 32768 257*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llihl [[REG2:%r[0-5]]], 65535 258*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llihh [[REG3:%r[0-5]]], 1 259*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llihh [[REG4:%r[0-5]]], 65535 260*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG1]], [[REG2]], [[REG3]], [[REG4]] 261*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llill [[REG1:%r[0-5]]], 32769 262*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llill [[REG2:%r[0-5]]], 65534 263*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llilh [[REG3:%r[0-5]]], 2 264*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llilh [[REG4:%r[0-5]]], 65534 265*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG1]], [[REG2]], [[REG3]], [[REG4]] 266*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llihl [[REG1:%r[0-5]]], 32770 267*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: iilf [[REG1]], 65533 268*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: llihh [[REG2:%r[0-5]]], 4 269*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: iilf [[REG2]], 524288 270*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG1]], [[REG1]], [[REG2]], [[REG2]] 271*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: iihf [[REG1:%r[0-5]]], 3294967296 272*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: iilf [[REG2:%r[0-5]]], 4294567296 273*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: iihf [[REG3:%r[0-5]]], 1000000000 274*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: iilf [[REG4:%r[0-5]]], 400000 275*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG1]], [[REG2]], [[REG3]], [[REG4]] 276*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 277*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepa $0, $1, $2, $3", 278*9880d681SAndroid Build Coastguard Worker "h,h,h,h"(i32 32768, i32 65535, 279*9880d681SAndroid Build Coastguard Worker i32 65536, i32 -65536) 280*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepb $0, $1, $2, $3", 281*9880d681SAndroid Build Coastguard Worker "r,r,r,r"(i32 32769, i32 65534, 282*9880d681SAndroid Build Coastguard Worker i32 131072, i32 -131072) 283*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepc $0, $1, $2, $3", 284*9880d681SAndroid Build Coastguard Worker "h,r,h,r"(i32 32770, i32 65533, 285*9880d681SAndroid Build Coastguard Worker i32 262144, i32 524288) 286*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepd $0, $1, $2, $3", 287*9880d681SAndroid Build Coastguard Worker "h,r,h,r"(i32 -1000000000, i32 -400000, 288*9880d681SAndroid Build Coastguard Worker i32 1000000000, i32 400000) 289*9880d681SAndroid Build Coastguard Worker ret void 290*9880d681SAndroid Build Coastguard Worker} 291*9880d681SAndroid Build Coastguard Worker 292*9880d681SAndroid Build Coastguard Worker; Test selects involving high registers. 293*9880d681SAndroid Build Coastguard Workerdefine void @f13(i32 %x, i32 %y) { 294*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f13: 295*9880d681SAndroid Build Coastguard Worker; CHECK: llihl [[REG:%r[0-5]]], 0 296*9880d681SAndroid Build Coastguard Worker; CHECK: cije %r2, 0 297*9880d681SAndroid Build Coastguard Worker; CHECK: iihf [[REG]], 2102030405 298*9880d681SAndroid Build Coastguard Worker; CHECK: blah [[REG]] 299*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 300*9880d681SAndroid Build Coastguard Worker %cmp = icmp eq i32 %x, 0 301*9880d681SAndroid Build Coastguard Worker %val = select i1 %cmp, i32 0, i32 2102030405 302*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "blah $0", "h"(i32 %val) 303*9880d681SAndroid Build Coastguard Worker ret void 304*9880d681SAndroid Build Coastguard Worker} 305*9880d681SAndroid Build Coastguard Worker 306*9880d681SAndroid Build Coastguard Worker; Test selects involving low registers. 307*9880d681SAndroid Build Coastguard Workerdefine void @f14(i32 %x, i32 %y) { 308*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f14: 309*9880d681SAndroid Build Coastguard Worker; CHECK: lhi [[REG:%r[0-5]]], 0 310*9880d681SAndroid Build Coastguard Worker; CHECK: cije %r2, 0 311*9880d681SAndroid Build Coastguard Worker; CHECK: iilf [[REG]], 2102030405 312*9880d681SAndroid Build Coastguard Worker; CHECK: blah [[REG]] 313*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 314*9880d681SAndroid Build Coastguard Worker %cmp = icmp eq i32 %x, 0 315*9880d681SAndroid Build Coastguard Worker %val = select i1 %cmp, i32 0, i32 2102030405 316*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "blah $0", "r"(i32 %val) 317*9880d681SAndroid Build Coastguard Worker ret void 318*9880d681SAndroid Build Coastguard Worker} 319*9880d681SAndroid Build Coastguard Worker 320*9880d681SAndroid Build Coastguard Worker; Test immediate insertion involving high registers. 321*9880d681SAndroid Build Coastguard Workerdefine void @f15() { 322*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f15: 323*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 324*9880d681SAndroid Build Coastguard Worker; CHECK: iihh [[REG]], 4660 325*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 326*9880d681SAndroid Build Coastguard Worker; CHECK: iihl [[REG]], 34661 327*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 328*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 329*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=h"() 330*9880d681SAndroid Build Coastguard Worker %and1 = and i32 %res1, 65535 331*9880d681SAndroid Build Coastguard Worker %or1 = or i32 %and1, 305397760 332*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %or1) 333*9880d681SAndroid Build Coastguard Worker %and2 = and i32 %res2, -65536 334*9880d681SAndroid Build Coastguard Worker %or2 = or i32 %and2, 34661 335*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepc $0", "h"(i32 %or2) 336*9880d681SAndroid Build Coastguard Worker ret void 337*9880d681SAndroid Build Coastguard Worker} 338*9880d681SAndroid Build Coastguard Worker 339*9880d681SAndroid Build Coastguard Worker; Test immediate insertion involving low registers. 340*9880d681SAndroid Build Coastguard Workerdefine void @f16() { 341*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f16: 342*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 343*9880d681SAndroid Build Coastguard Worker; CHECK: iilh [[REG]], 4660 344*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 345*9880d681SAndroid Build Coastguard Worker; CHECK: iill [[REG]], 34661 346*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 347*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 348*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=r"() 349*9880d681SAndroid Build Coastguard Worker %and1 = and i32 %res1, 65535 350*9880d681SAndroid Build Coastguard Worker %or1 = or i32 %and1, 305397760 351*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %or1) 352*9880d681SAndroid Build Coastguard Worker %and2 = and i32 %res2, -65536 353*9880d681SAndroid Build Coastguard Worker %or2 = or i32 %and2, 34661 354*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepc $0", "r"(i32 %or2) 355*9880d681SAndroid Build Coastguard Worker ret void 356*9880d681SAndroid Build Coastguard Worker} 357*9880d681SAndroid Build Coastguard Worker 358*9880d681SAndroid Build Coastguard Worker; Test immediate OR involving high registers. 359*9880d681SAndroid Build Coastguard Workerdefine void @f17() { 360*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f17: 361*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 362*9880d681SAndroid Build Coastguard Worker; CHECK: oihh [[REG]], 4660 363*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 364*9880d681SAndroid Build Coastguard Worker; CHECK: oihl [[REG]], 34661 365*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 366*9880d681SAndroid Build Coastguard Worker; CHECK: oihf [[REG]], 12345678 367*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG]] 368*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 369*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=h"() 370*9880d681SAndroid Build Coastguard Worker %or1 = or i32 %res1, 305397760 371*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %or1) 372*9880d681SAndroid Build Coastguard Worker %or2 = or i32 %res2, 34661 373*9880d681SAndroid Build Coastguard Worker %res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %or2) 374*9880d681SAndroid Build Coastguard Worker %or3 = or i32 %res3, 12345678 375*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepd $0", "h"(i32 %or3) 376*9880d681SAndroid Build Coastguard Worker ret void 377*9880d681SAndroid Build Coastguard Worker} 378*9880d681SAndroid Build Coastguard Worker 379*9880d681SAndroid Build Coastguard Worker; Test immediate OR involving low registers. 380*9880d681SAndroid Build Coastguard Workerdefine void @f18() { 381*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f18: 382*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 383*9880d681SAndroid Build Coastguard Worker; CHECK: oilh [[REG]], 4660 384*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 385*9880d681SAndroid Build Coastguard Worker; CHECK: oill [[REG]], 34661 386*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 387*9880d681SAndroid Build Coastguard Worker; CHECK: oilf [[REG]], 12345678 388*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG]] 389*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 390*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=r"() 391*9880d681SAndroid Build Coastguard Worker %or1 = or i32 %res1, 305397760 392*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %or1) 393*9880d681SAndroid Build Coastguard Worker %or2 = or i32 %res2, 34661 394*9880d681SAndroid Build Coastguard Worker %res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %or2) 395*9880d681SAndroid Build Coastguard Worker %or3 = or i32 %res3, 12345678 396*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepd $0", "r"(i32 %or3) 397*9880d681SAndroid Build Coastguard Worker ret void 398*9880d681SAndroid Build Coastguard Worker} 399*9880d681SAndroid Build Coastguard Worker 400*9880d681SAndroid Build Coastguard Worker; Test immediate XOR involving high registers. 401*9880d681SAndroid Build Coastguard Workerdefine void @f19() { 402*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f19: 403*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 404*9880d681SAndroid Build Coastguard Worker; CHECK: xihf [[REG]], 305397760 405*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 406*9880d681SAndroid Build Coastguard Worker; CHECK: xihf [[REG]], 34661 407*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 408*9880d681SAndroid Build Coastguard Worker; CHECK: xihf [[REG]], 12345678 409*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG]] 410*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 411*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=h"() 412*9880d681SAndroid Build Coastguard Worker %xor1 = xor i32 %res1, 305397760 413*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %xor1) 414*9880d681SAndroid Build Coastguard Worker %xor2 = xor i32 %res2, 34661 415*9880d681SAndroid Build Coastguard Worker %res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %xor2) 416*9880d681SAndroid Build Coastguard Worker %xor3 = xor i32 %res3, 12345678 417*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepd $0", "h"(i32 %xor3) 418*9880d681SAndroid Build Coastguard Worker ret void 419*9880d681SAndroid Build Coastguard Worker} 420*9880d681SAndroid Build Coastguard Worker 421*9880d681SAndroid Build Coastguard Worker; Test immediate XOR involving low registers. 422*9880d681SAndroid Build Coastguard Workerdefine void @f20() { 423*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f20: 424*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 425*9880d681SAndroid Build Coastguard Worker; CHECK: xilf [[REG]], 305397760 426*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 427*9880d681SAndroid Build Coastguard Worker; CHECK: xilf [[REG]], 34661 428*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 429*9880d681SAndroid Build Coastguard Worker; CHECK: xilf [[REG]], 12345678 430*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG]] 431*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 432*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=r"() 433*9880d681SAndroid Build Coastguard Worker %xor1 = xor i32 %res1, 305397760 434*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %xor1) 435*9880d681SAndroid Build Coastguard Worker %xor2 = xor i32 %res2, 34661 436*9880d681SAndroid Build Coastguard Worker %res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %xor2) 437*9880d681SAndroid Build Coastguard Worker %xor3 = xor i32 %res3, 12345678 438*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepd $0", "r"(i32 %xor3) 439*9880d681SAndroid Build Coastguard Worker ret void 440*9880d681SAndroid Build Coastguard Worker} 441*9880d681SAndroid Build Coastguard Worker 442*9880d681SAndroid Build Coastguard Worker; Test two-operand immediate AND involving high registers. 443*9880d681SAndroid Build Coastguard Workerdefine void @f21() { 444*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f21: 445*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 446*9880d681SAndroid Build Coastguard Worker; CHECK: nihh [[REG]], 4096 447*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 448*9880d681SAndroid Build Coastguard Worker; CHECK: nihl [[REG]], 57536 449*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 450*9880d681SAndroid Build Coastguard Worker; CHECK: nihf [[REG]], 12345678 451*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG]] 452*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 453*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=h"() 454*9880d681SAndroid Build Coastguard Worker %and1 = and i32 %res1, 268500991 455*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %and1) 456*9880d681SAndroid Build Coastguard Worker %and2 = and i32 %res2, -8000 457*9880d681SAndroid Build Coastguard Worker %res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %and2) 458*9880d681SAndroid Build Coastguard Worker %and3 = and i32 %res3, 12345678 459*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepd $0", "h"(i32 %and3) 460*9880d681SAndroid Build Coastguard Worker ret void 461*9880d681SAndroid Build Coastguard Worker} 462*9880d681SAndroid Build Coastguard Worker 463*9880d681SAndroid Build Coastguard Worker; Test two-operand immediate AND involving low registers. 464*9880d681SAndroid Build Coastguard Workerdefine void @f22() { 465*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f22: 466*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 467*9880d681SAndroid Build Coastguard Worker; CHECK: nilh [[REG]], 4096 468*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 469*9880d681SAndroid Build Coastguard Worker; CHECK: nill [[REG]], 57536 470*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 471*9880d681SAndroid Build Coastguard Worker; CHECK: nilf [[REG]], 12345678 472*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG]] 473*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 474*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=r"() 475*9880d681SAndroid Build Coastguard Worker %and1 = and i32 %res1, 268500991 476*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %and1) 477*9880d681SAndroid Build Coastguard Worker %and2 = and i32 %res2, -8000 478*9880d681SAndroid Build Coastguard Worker %res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %and2) 479*9880d681SAndroid Build Coastguard Worker %and3 = and i32 %res3, 12345678 480*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepd $0", "r"(i32 %and3) 481*9880d681SAndroid Build Coastguard Worker ret void 482*9880d681SAndroid Build Coastguard Worker} 483*9880d681SAndroid Build Coastguard Worker 484*9880d681SAndroid Build Coastguard Worker; Test three-operand immediate AND involving mixtures of low and high registers. 485*9880d681SAndroid Build Coastguard Workerdefine i32 @f23(i32 %old) { 486*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f23: 487*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: risblg [[REG1:%r[0-5]]], %r2, 28, 158, 0 488*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: risbhg [[REG2:%r[0-5]]], %r2, 24, 158, 32 489*9880d681SAndroid Build Coastguard Worker; CHECK: stepa %r2, [[REG1]], [[REG2]] 490*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: risbhg [[REG3:%r[0-5]]], [[REG2]], 25, 159, 0 491*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: risblg %r2, [[REG2]], 24, 152, 32 492*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG2]], [[REG3]], %r2 493*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 494*9880d681SAndroid Build Coastguard Worker %and1 = and i32 %old, 14 495*9880d681SAndroid Build Coastguard Worker %and2 = and i32 %old, 254 496*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $1, $2, $3", 497*9880d681SAndroid Build Coastguard Worker "=h,r,r,0"(i32 %old, i32 %and1, i32 %and2) 498*9880d681SAndroid Build Coastguard Worker %and3 = and i32 %res1, 127 499*9880d681SAndroid Build Coastguard Worker %and4 = and i32 %res1, 128 500*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $1, $2, $3", 501*9880d681SAndroid Build Coastguard Worker "=r,h,h,0"(i32 %res1, i32 %and3, i32 %and4) 502*9880d681SAndroid Build Coastguard Worker ret i32 %res2 503*9880d681SAndroid Build Coastguard Worker} 504*9880d681SAndroid Build Coastguard Worker 505*9880d681SAndroid Build Coastguard Worker; Test RISB[LH]G insertions involving mixtures of high and low registers. 506*9880d681SAndroid Build Coastguard Workerdefine i32 @f24(i32 %old) { 507*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f24: 508*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: risblg [[REG1:%r[0-5]]], %r2, 28, 158, 1 509*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: risbhg [[REG2:%r[0-5]]], %r2, 24, 158, 29 510*9880d681SAndroid Build Coastguard Worker; CHECK: stepa %r2, [[REG1]], [[REG2]] 511*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: risbhg [[REG3:%r[0-5]]], [[REG2]], 25, 159, 62 512*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: risblg %r2, [[REG2]], 24, 152, 37 513*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG2]], [[REG3]], %r2 514*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 515*9880d681SAndroid Build Coastguard Worker %shift1 = shl i32 %old, 1 516*9880d681SAndroid Build Coastguard Worker %and1 = and i32 %shift1, 14 517*9880d681SAndroid Build Coastguard Worker %shift2 = lshr i32 %old, 3 518*9880d681SAndroid Build Coastguard Worker %and2 = and i32 %shift2, 254 519*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $1, $2, $3", 520*9880d681SAndroid Build Coastguard Worker "=h,r,r,0"(i32 %old, i32 %and1, i32 %and2) 521*9880d681SAndroid Build Coastguard Worker %shift3 = lshr i32 %res1, 2 522*9880d681SAndroid Build Coastguard Worker %and3 = and i32 %shift3, 127 523*9880d681SAndroid Build Coastguard Worker %shift4 = shl i32 %res1, 5 524*9880d681SAndroid Build Coastguard Worker %and4 = and i32 %shift4, 128 525*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $1, $2, $3", 526*9880d681SAndroid Build Coastguard Worker "=r,h,h,0"(i32 %res1, i32 %and3, i32 %and4) 527*9880d681SAndroid Build Coastguard Worker ret i32 %res2 528*9880d681SAndroid Build Coastguard Worker} 529*9880d681SAndroid Build Coastguard Worker 530*9880d681SAndroid Build Coastguard Worker; Test TMxx involving mixtures of high and low registers. 531*9880d681SAndroid Build Coastguard Workerdefine i32 @f25(i32 %old) { 532*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f25: 533*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: tmll %r2, 1 534*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: tmlh %r2, 1 535*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG1:%r[0-5]]], 536*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: tmhl [[REG1]], 1 537*9880d681SAndroid Build Coastguard Worker; CHECK-DAG: tmhh [[REG1]], 1 538*9880d681SAndroid Build Coastguard Worker; CHECK: stepb %r2, 539*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 540*9880d681SAndroid Build Coastguard Worker %and1 = and i32 %old, 1 541*9880d681SAndroid Build Coastguard Worker %and2 = and i32 %old, 65536 542*9880d681SAndroid Build Coastguard Worker %cmp1 = icmp eq i32 %and1, 0 543*9880d681SAndroid Build Coastguard Worker %cmp2 = icmp eq i32 %and2, 0 544*9880d681SAndroid Build Coastguard Worker %sel1 = select i1 %cmp1, i32 100, i32 200 545*9880d681SAndroid Build Coastguard Worker %sel2 = select i1 %cmp2, i32 100, i32 200 546*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0, $1, $2", 547*9880d681SAndroid Build Coastguard Worker "=h,r,r"(i32 %sel1, i32 %sel2) 548*9880d681SAndroid Build Coastguard Worker %and3 = and i32 %res1, 1 549*9880d681SAndroid Build Coastguard Worker %and4 = and i32 %res1, 65536 550*9880d681SAndroid Build Coastguard Worker %cmp3 = icmp eq i32 %and3, 0 551*9880d681SAndroid Build Coastguard Worker %cmp4 = icmp eq i32 %and4, 0 552*9880d681SAndroid Build Coastguard Worker %sel3 = select i1 %cmp3, i32 100, i32 200 553*9880d681SAndroid Build Coastguard Worker %sel4 = select i1 %cmp4, i32 100, i32 200 554*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1, $2", 555*9880d681SAndroid Build Coastguard Worker "=r,h,h"(i32 %sel3, i32 %sel4) 556*9880d681SAndroid Build Coastguard Worker ret i32 %res2 557*9880d681SAndroid Build Coastguard Worker} 558*9880d681SAndroid Build Coastguard Worker 559*9880d681SAndroid Build Coastguard Worker; Test two-operand halfword immediate addition involving high registers. 560*9880d681SAndroid Build Coastguard Workerdefine void @f26() { 561*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f26: 562*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 563*9880d681SAndroid Build Coastguard Worker; CHECK: aih [[REG]], -32768 564*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 565*9880d681SAndroid Build Coastguard Worker; CHECK: aih [[REG]], 1 566*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 567*9880d681SAndroid Build Coastguard Worker; CHECK: aih [[REG]], 32767 568*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG]] 569*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 570*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=h"() 571*9880d681SAndroid Build Coastguard Worker %add1 = add i32 %res1, -32768 572*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %add1) 573*9880d681SAndroid Build Coastguard Worker %add2 = add i32 %res2, 1 574*9880d681SAndroid Build Coastguard Worker %res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %add2) 575*9880d681SAndroid Build Coastguard Worker %add3 = add i32 %res3, 32767 576*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepd $0", "h"(i32 %add3) 577*9880d681SAndroid Build Coastguard Worker ret void 578*9880d681SAndroid Build Coastguard Worker} 579*9880d681SAndroid Build Coastguard Worker 580*9880d681SAndroid Build Coastguard Worker; Test two-operand halfword immediate addition involving low registers. 581*9880d681SAndroid Build Coastguard Workerdefine void @f27() { 582*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f27: 583*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 584*9880d681SAndroid Build Coastguard Worker; CHECK: ahi [[REG]], -32768 585*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 586*9880d681SAndroid Build Coastguard Worker; CHECK: ahi [[REG]], 1 587*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 588*9880d681SAndroid Build Coastguard Worker; CHECK: ahi [[REG]], 32767 589*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG]] 590*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 591*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=r"() 592*9880d681SAndroid Build Coastguard Worker %add1 = add i32 %res1, -32768 593*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %add1) 594*9880d681SAndroid Build Coastguard Worker %add2 = add i32 %res2, 1 595*9880d681SAndroid Build Coastguard Worker %res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %add2) 596*9880d681SAndroid Build Coastguard Worker %add3 = add i32 %res3, 32767 597*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepd $0", "r"(i32 %add3) 598*9880d681SAndroid Build Coastguard Worker ret void 599*9880d681SAndroid Build Coastguard Worker} 600*9880d681SAndroid Build Coastguard Worker 601*9880d681SAndroid Build Coastguard Worker; Test three-operand halfword immediate addition involving mixtures of low 602*9880d681SAndroid Build Coastguard Worker; and high registers. RISBHG/AIH would be OK too, instead of AHIK/RISBHG. 603*9880d681SAndroid Build Coastguard Workerdefine i32 @f28(i32 %old) { 604*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f28: 605*9880d681SAndroid Build Coastguard Worker; CHECK: ahik [[REG1:%r[0-5]]], %r2, 14 606*9880d681SAndroid Build Coastguard Worker; CHECK: stepa %r2, [[REG1]] 607*9880d681SAndroid Build Coastguard Worker; CHECK: ahik [[TMP:%r[0-5]]], [[REG1]], 254 608*9880d681SAndroid Build Coastguard Worker; CHECK: risbhg [[REG2:%r[0-5]]], [[TMP]], 0, 159, 32 609*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG1]], [[REG2]] 610*9880d681SAndroid Build Coastguard Worker; CHECK: risbhg [[REG3:%r[0-5]]], [[REG2]], 0, 159, 0 611*9880d681SAndroid Build Coastguard Worker; CHECK: aih [[REG3]], 127 612*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG2]], [[REG3]] 613*9880d681SAndroid Build Coastguard Worker; CHECK: risblg %r2, [[REG3]], 0, 159, 32 614*9880d681SAndroid Build Coastguard Worker; CHECK: ahi %r2, 128 615*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG3]], %r2 616*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 617*9880d681SAndroid Build Coastguard Worker %add1 = add i32 %old, 14 618*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $1, $2", 619*9880d681SAndroid Build Coastguard Worker "=r,r,0"(i32 %old, i32 %add1) 620*9880d681SAndroid Build Coastguard Worker %add2 = add i32 %res1, 254 621*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $1, $2", 622*9880d681SAndroid Build Coastguard Worker "=h,r,0"(i32 %res1, i32 %add2) 623*9880d681SAndroid Build Coastguard Worker %add3 = add i32 %res2, 127 624*9880d681SAndroid Build Coastguard Worker %res3 = call i32 asm "stepc $1, $2", 625*9880d681SAndroid Build Coastguard Worker "=h,h,0"(i32 %res2, i32 %add3) 626*9880d681SAndroid Build Coastguard Worker %add4 = add i32 %res3, 128 627*9880d681SAndroid Build Coastguard Worker %res4 = call i32 asm "stepd $1, $2", 628*9880d681SAndroid Build Coastguard Worker "=r,h,0"(i32 %res3, i32 %add4) 629*9880d681SAndroid Build Coastguard Worker ret i32 %res4 630*9880d681SAndroid Build Coastguard Worker} 631*9880d681SAndroid Build Coastguard Worker 632*9880d681SAndroid Build Coastguard Worker; Test large immediate addition involving high registers. 633*9880d681SAndroid Build Coastguard Workerdefine void @f29() { 634*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f29: 635*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 636*9880d681SAndroid Build Coastguard Worker; CHECK: aih [[REG]], -32769 637*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 638*9880d681SAndroid Build Coastguard Worker; CHECK: aih [[REG]], 32768 639*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 640*9880d681SAndroid Build Coastguard Worker; CHECK: aih [[REG]], 1000000000 641*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG]] 642*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 643*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=h"() 644*9880d681SAndroid Build Coastguard Worker %add1 = add i32 %res1, -32769 645*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %add1) 646*9880d681SAndroid Build Coastguard Worker %add2 = add i32 %res2, 32768 647*9880d681SAndroid Build Coastguard Worker %res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %add2) 648*9880d681SAndroid Build Coastguard Worker %add3 = add i32 %res3, 1000000000 649*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepd $0", "h"(i32 %add3) 650*9880d681SAndroid Build Coastguard Worker ret void 651*9880d681SAndroid Build Coastguard Worker} 652*9880d681SAndroid Build Coastguard Worker 653*9880d681SAndroid Build Coastguard Worker; Test large immediate addition involving low registers. 654*9880d681SAndroid Build Coastguard Workerdefine void @f30() { 655*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f30: 656*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG:%r[0-5]]] 657*9880d681SAndroid Build Coastguard Worker; CHECK: afi [[REG]], -32769 658*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG]] 659*9880d681SAndroid Build Coastguard Worker; CHECK: afi [[REG]], 32768 660*9880d681SAndroid Build Coastguard Worker; CHECK: stepc [[REG]] 661*9880d681SAndroid Build Coastguard Worker; CHECK: afi [[REG]], 1000000000 662*9880d681SAndroid Build Coastguard Worker; CHECK: stepd [[REG]] 663*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 664*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=r"() 665*9880d681SAndroid Build Coastguard Worker %add1 = add i32 %res1, -32769 666*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %add1) 667*9880d681SAndroid Build Coastguard Worker %add2 = add i32 %res2, 32768 668*9880d681SAndroid Build Coastguard Worker %res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %add2) 669*9880d681SAndroid Build Coastguard Worker %add3 = add i32 %res3, 1000000000 670*9880d681SAndroid Build Coastguard Worker call void asm sideeffect "stepd $0", "r"(i32 %add3) 671*9880d681SAndroid Build Coastguard Worker ret void 672*9880d681SAndroid Build Coastguard Worker} 673*9880d681SAndroid Build Coastguard Worker 674*9880d681SAndroid Build Coastguard Worker; Test large immediate comparison involving high registers. 675*9880d681SAndroid Build Coastguard Workerdefine i32 @f31() { 676*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f31: 677*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG1:%r[0-5]]] 678*9880d681SAndroid Build Coastguard Worker; CHECK: cih [[REG1]], 1000000000 679*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG2:%r[0-5]]] 680*9880d681SAndroid Build Coastguard Worker; CHECK: clih [[REG2]], 1000000000 681*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 682*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=h"() 683*9880d681SAndroid Build Coastguard Worker %cmp1 = icmp sle i32 %res1, 1000000000 684*9880d681SAndroid Build Coastguard Worker %sel1 = select i1 %cmp1, i32 0, i32 1 685*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1) 686*9880d681SAndroid Build Coastguard Worker %cmp2 = icmp ule i32 %res2, 1000000000 687*9880d681SAndroid Build Coastguard Worker %sel2 = select i1 %cmp2, i32 0, i32 1 688*9880d681SAndroid Build Coastguard Worker ret i32 %sel2 689*9880d681SAndroid Build Coastguard Worker} 690*9880d681SAndroid Build Coastguard Worker 691*9880d681SAndroid Build Coastguard Worker; Test large immediate comparison involving low registers. 692*9880d681SAndroid Build Coastguard Workerdefine i32 @f32() { 693*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f32: 694*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG1:%r[0-5]]] 695*9880d681SAndroid Build Coastguard Worker; CHECK: cfi [[REG1]], 1000000000 696*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG2:%r[0-5]]] 697*9880d681SAndroid Build Coastguard Worker; CHECK: clfi [[REG2]], 1000000000 698*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 699*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=r"() 700*9880d681SAndroid Build Coastguard Worker %cmp1 = icmp sle i32 %res1, 1000000000 701*9880d681SAndroid Build Coastguard Worker %sel1 = select i1 %cmp1, i32 0, i32 1 702*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1) 703*9880d681SAndroid Build Coastguard Worker %cmp2 = icmp ule i32 %res2, 1000000000 704*9880d681SAndroid Build Coastguard Worker %sel2 = select i1 %cmp2, i32 0, i32 1 705*9880d681SAndroid Build Coastguard Worker ret i32 %sel2 706*9880d681SAndroid Build Coastguard Worker} 707*9880d681SAndroid Build Coastguard Worker 708*9880d681SAndroid Build Coastguard Worker; Test memory comparison involving high registers. 709*9880d681SAndroid Build Coastguard Workerdefine void @f33(i32 *%ptr1, i32 *%ptr2) { 710*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f33: 711*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG1:%r[0-5]]] 712*9880d681SAndroid Build Coastguard Worker; CHECK: chf [[REG1]], 0(%r2) 713*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG2:%r[0-5]]] 714*9880d681SAndroid Build Coastguard Worker; CHECK: clhf [[REG2]], 0(%r3) 715*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 716*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=h"() 717*9880d681SAndroid Build Coastguard Worker %load1 = load i32 , i32 *%ptr1 718*9880d681SAndroid Build Coastguard Worker %cmp1 = icmp sle i32 %res1, %load1 719*9880d681SAndroid Build Coastguard Worker %sel1 = select i1 %cmp1, i32 0, i32 1 720*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=h,r"(i32 %sel1) 721*9880d681SAndroid Build Coastguard Worker %load2 = load i32 , i32 *%ptr2 722*9880d681SAndroid Build Coastguard Worker %cmp2 = icmp ule i32 %res2, %load2 723*9880d681SAndroid Build Coastguard Worker %sel2 = select i1 %cmp2, i32 0, i32 1 724*9880d681SAndroid Build Coastguard Worker store i32 %sel2, i32 *%ptr1 725*9880d681SAndroid Build Coastguard Worker ret void 726*9880d681SAndroid Build Coastguard Worker} 727*9880d681SAndroid Build Coastguard Worker 728*9880d681SAndroid Build Coastguard Worker; Test memory comparison involving low registers. 729*9880d681SAndroid Build Coastguard Workerdefine void @f34(i32 *%ptr1, i32 *%ptr2) { 730*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: f34: 731*9880d681SAndroid Build Coastguard Worker; CHECK: stepa [[REG1:%r[0-5]]] 732*9880d681SAndroid Build Coastguard Worker; CHECK: c [[REG1]], 0(%r2) 733*9880d681SAndroid Build Coastguard Worker; CHECK: stepb [[REG2:%r[0-5]]] 734*9880d681SAndroid Build Coastguard Worker; CHECK: cl [[REG2]], 0(%r3) 735*9880d681SAndroid Build Coastguard Worker; CHECK: br %r14 736*9880d681SAndroid Build Coastguard Worker %res1 = call i32 asm "stepa $0", "=r"() 737*9880d681SAndroid Build Coastguard Worker %load1 = load i32 , i32 *%ptr1 738*9880d681SAndroid Build Coastguard Worker %cmp1 = icmp sle i32 %res1, %load1 739*9880d681SAndroid Build Coastguard Worker %sel1 = select i1 %cmp1, i32 0, i32 1 740*9880d681SAndroid Build Coastguard Worker %res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %sel1) 741*9880d681SAndroid Build Coastguard Worker %load2 = load i32 , i32 *%ptr2 742*9880d681SAndroid Build Coastguard Worker %cmp2 = icmp ule i32 %res2, %load2 743*9880d681SAndroid Build Coastguard Worker %sel2 = select i1 %cmp2, i32 0, i32 1 744*9880d681SAndroid Build Coastguard Worker store i32 %sel2, i32 *%ptr1 745*9880d681SAndroid Build Coastguard Worker ret void 746*9880d681SAndroid Build Coastguard Worker} 747