1*9880d681SAndroid Build Coastguard Worker; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs < %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s | FileCheck %s 3*9880d681SAndroid Build Coastguard Worker; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-VSX %s 4*9880d681SAndroid Build Coastguard Worker 5*9880d681SAndroid Build Coastguard Worker; This verifies that we generate correct spill/reload code for vector regs. 6*9880d681SAndroid Build Coastguard Worker 7*9880d681SAndroid Build Coastguard Workerdefine void @addrtaken(i32 %i, <4 x float> %w) nounwind { 8*9880d681SAndroid Build Coastguard Workerentry: 9*9880d681SAndroid Build Coastguard Worker %i.addr = alloca i32, align 4 10*9880d681SAndroid Build Coastguard Worker %w.addr = alloca <4 x float>, align 16 11*9880d681SAndroid Build Coastguard Worker store i32 %i, i32* %i.addr, align 4 12*9880d681SAndroid Build Coastguard Worker store <4 x float> %w, <4 x float>* %w.addr, align 16 13*9880d681SAndroid Build Coastguard Worker call void @foo(i32* %i.addr) 14*9880d681SAndroid Build Coastguard Worker ret void 15*9880d681SAndroid Build Coastguard Worker} 16*9880d681SAndroid Build Coastguard Worker 17*9880d681SAndroid Build Coastguard Worker; CHECK: stvx 2, 18*9880d681SAndroid Build Coastguard Worker 19*9880d681SAndroid Build Coastguard Worker; We would prefer to test for "stxvw4x 34," but current -O0 code 20*9880d681SAndroid Build Coastguard Worker; needlessly generates "vor 3,2,2 / stxvw4x 35,0,3", so we'll settle for 21*9880d681SAndroid Build Coastguard Worker; the opcode. 22*9880d681SAndroid Build Coastguard Worker; CHECK-VSX: stxvw4x 23*9880d681SAndroid Build Coastguard Worker 24*9880d681SAndroid Build Coastguard Workerdeclare void @foo(i32*) 25