1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Workertarget datalayout = "e-m:e-i64:64-n32:64" 3*9880d681SAndroid Build Coastguard Workertarget triple = "powerpc64le" 4*9880d681SAndroid Build Coastguard Worker 5*9880d681SAndroid Build Coastguard Worker; Function Attrs: nounwind 6*9880d681SAndroid Build Coastguard Workerdefine void @test_vsx() unnamed_addr #0 align 2 { 7*9880d681SAndroid Build Coastguard Workerentry: 8*9880d681SAndroid Build Coastguard Worker %0 = load i32, i32* undef, align 4 9*9880d681SAndroid Build Coastguard Worker %1 = trunc i32 %0 to i8 10*9880d681SAndroid Build Coastguard Worker call void @llvm.memset.p0i8.i64(i8* null, i8 %1, i64 32, i32 1, i1 false) 11*9880d681SAndroid Build Coastguard Worker ret void 12*9880d681SAndroid Build Coastguard Worker 13*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: @test_vsx 14*9880d681SAndroid Build Coastguard Worker; CHECK: stxvd2x 15*9880d681SAndroid Build Coastguard Worker; CHECK: stxvd2x 16*9880d681SAndroid Build Coastguard Worker; CHECK: blr 17*9880d681SAndroid Build Coastguard Worker} 18*9880d681SAndroid Build Coastguard Worker 19*9880d681SAndroid Build Coastguard Worker; Function Attrs: nounwind 20*9880d681SAndroid Build Coastguard Workerdeclare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1 21*9880d681SAndroid Build Coastguard Worker 22*9880d681SAndroid Build Coastguard Workerattributes #0 = { nounwind "target-cpu"="pwr8" } 23*9880d681SAndroid Build Coastguard Workerattributes #1 = { nounwind } 24*9880d681SAndroid Build Coastguard Worker 25