xref: /aosp_15_r20/external/llvm/test/CodeGen/PowerPC/dcbt-sched.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58)
1*9880d681SAndroid Build Coastguard Workertarget datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
2*9880d681SAndroid Build Coastguard Workertarget triple = "powerpc64-unknown-linux-gnu"
3*9880d681SAndroid Build Coastguard Worker; RUN: llc -mcpu=a2 -enable-misched -enable-aa-sched-mi < %s | FileCheck %s
4*9880d681SAndroid Build Coastguard Worker
5*9880d681SAndroid Build Coastguard Workerdefine i8 @test1(i8* noalias %a, i8* noalias %b, i8* noalias %c) nounwind {
6*9880d681SAndroid Build Coastguard Workerentry:
7*9880d681SAndroid Build Coastguard Worker  %q = load i8, i8* %b
8*9880d681SAndroid Build Coastguard Worker  call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 1)
9*9880d681SAndroid Build Coastguard Worker  %r = load i8, i8* %c
10*9880d681SAndroid Build Coastguard Worker  %s = add i8 %q, %r
11*9880d681SAndroid Build Coastguard Worker  ret i8 %s
12*9880d681SAndroid Build Coastguard Worker}
13*9880d681SAndroid Build Coastguard Worker
14*9880d681SAndroid Build Coastguard Workerdeclare void @llvm.prefetch(i8*, i32, i32, i32)
15*9880d681SAndroid Build Coastguard Worker
16*9880d681SAndroid Build Coastguard Worker; Test that we've moved the second load to before the dcbt to better
17*9880d681SAndroid Build Coastguard Worker; hide its latency.
18*9880d681SAndroid Build Coastguard Worker; CHECK: @test1
19*9880d681SAndroid Build Coastguard Worker; CHECK: lbz
20*9880d681SAndroid Build Coastguard Worker; CHECK: lbz
21*9880d681SAndroid Build Coastguard Worker; CHECK: dcbt
22*9880d681SAndroid Build Coastguard Worker
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