1*9880d681SAndroid Build Coastguard Worker; RUN: llc -mattr=-vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; RUN: llc -mattr=+vsx -mattr=+altivec -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-VSX %s 3*9880d681SAndroid Build Coastguard Workertarget datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" 4*9880d681SAndroid Build Coastguard Workertarget triple = "powerpc64-unknown-linux-gnu" 5*9880d681SAndroid Build Coastguard Worker 6*9880d681SAndroid Build Coastguard Workerdefine i32 @test(<16 x i8> %v) nounwind { 7*9880d681SAndroid Build Coastguard Workerentry: 8*9880d681SAndroid Build Coastguard Worker %0 = bitcast <16 x i8> %v to i128 9*9880d681SAndroid Build Coastguard Worker %1 = lshr i128 %0, 96 10*9880d681SAndroid Build Coastguard Worker %2 = trunc i128 %1 to i32 11*9880d681SAndroid Build Coastguard Worker ret i32 %2 12*9880d681SAndroid Build Coastguard Worker} 13*9880d681SAndroid Build Coastguard Worker 14*9880d681SAndroid Build Coastguard Worker; Verify that bitcast handles big-endian platforms correctly 15*9880d681SAndroid Build Coastguard Worker; by checking we load the result from the correct offset 16*9880d681SAndroid Build Coastguard Worker 17*9880d681SAndroid Build Coastguard Worker; CHECK: addi [[REGISTER:[0-9]+]], 1, -16 18*9880d681SAndroid Build Coastguard Worker; CHECK: stvx 2, 0, [[REGISTER]] 19*9880d681SAndroid Build Coastguard Worker; CHECK: lwz 3, -16(1) 20*9880d681SAndroid Build Coastguard Worker; CHECK: blr 21*9880d681SAndroid Build Coastguard Worker 22*9880d681SAndroid Build Coastguard Worker; CHECK-VSX: addi [[REGISTER:[0-9]+]], 1, -16 23*9880d681SAndroid Build Coastguard Worker; CHECK-VSX: stxvd2x 34, 0, [[REGISTER]] 24*9880d681SAndroid Build Coastguard Worker; CHECK-VSX: lwz 3, -16(1) 25*9880d681SAndroid Build Coastguard Worker; CHECK-VSX: blr 26