1*9880d681SAndroid Build Coastguard Worker; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT 2*9880d681SAndroid Build Coastguard Worker; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+nooddspreg < %s | FileCheck %s -check-prefixes=ALL,NOODDSPREG 3*9880d681SAndroid Build Coastguard Worker; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT 4*9880d681SAndroid Build Coastguard Worker; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64,+nooddspreg < %s | FileCheck %s -check-prefixes=ALL,NOODDSPREG 5*9880d681SAndroid Build Coastguard Worker; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fpxx,-nooddspreg < %s | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-EMIT 6*9880d681SAndroid Build Coastguard Worker 7*9880d681SAndroid Build Coastguard Worker; We don't emit a directive unless we need to. This is to support versions of 8*9880d681SAndroid Build Coastguard Worker; GAS which do not support the directive. 9*9880d681SAndroid Build Coastguard Worker; ODDSPREG-EMIT: .module oddspreg 10*9880d681SAndroid Build Coastguard Worker; ODDSPREG-NO-EMIT-NOT: .module oddspreg 11*9880d681SAndroid Build Coastguard Worker; NOODDSPREG: .module nooddspreg 12*9880d681SAndroid Build Coastguard Worker 13*9880d681SAndroid Build Coastguard Workerdefine float @two_floats(float %a) { 14*9880d681SAndroid Build Coastguard Workerentry: 15*9880d681SAndroid Build Coastguard Worker ; Clobber all except $f12 and $f13 16*9880d681SAndroid Build Coastguard Worker ; 17*9880d681SAndroid Build Coastguard Worker ; The intention is that if odd single precision registers are permitted, the 18*9880d681SAndroid Build Coastguard Worker ; allocator will choose $f12 and $f13 to avoid the spill/reload. 19*9880d681SAndroid Build Coastguard Worker ; 20*9880d681SAndroid Build Coastguard Worker ; On the other hand, if odd single precision registers are not permitted, it 21*9880d681SAndroid Build Coastguard Worker ; will be forced to spill/reload either %a or %0. 22*9880d681SAndroid Build Coastguard Worker 23*9880d681SAndroid Build Coastguard Worker %0 = fadd float %a, 1.0 24*9880d681SAndroid Build Coastguard Worker call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() 25*9880d681SAndroid Build Coastguard Worker %1 = fadd float %a, %0 26*9880d681SAndroid Build Coastguard Worker ret float %1 27*9880d681SAndroid Build Coastguard Worker} 28*9880d681SAndroid Build Coastguard Worker 29*9880d681SAndroid Build Coastguard Worker; ALL-LABEL: two_floats: 30*9880d681SAndroid Build Coastguard Worker; ODDSPREG: add.s $f13, $f12, ${{f[0-9]+}} 31*9880d681SAndroid Build Coastguard Worker; ODDSPREG-NOT: swc1 32*9880d681SAndroid Build Coastguard Worker; ODDSPREG-NOT: lwc1 33*9880d681SAndroid Build Coastguard Worker; ODDSPREG: add.s $f0, $f12, $f13 34*9880d681SAndroid Build Coastguard Worker 35*9880d681SAndroid Build Coastguard Worker; NOODDSPREG: add.s $[[T0:f[0-9]*[02468]]], $f12, ${{f[0-9]+}} 36*9880d681SAndroid Build Coastguard Worker; NOODDSPREG: swc1 $[[T0]], 37*9880d681SAndroid Build Coastguard Worker; NOODDSPREG: lwc1 $[[T1:f[0-9]*[02468]]], 38*9880d681SAndroid Build Coastguard Worker; NOODDSPREG: add.s $f0, $f12, $[[T1]] 39*9880d681SAndroid Build Coastguard Worker 40*9880d681SAndroid Build Coastguard Workerdefine double @two_doubles(double %a) { 41*9880d681SAndroid Build Coastguard Workerentry: 42*9880d681SAndroid Build Coastguard Worker ; Clobber all except $f12 and $f13 43*9880d681SAndroid Build Coastguard Worker ; 44*9880d681SAndroid Build Coastguard Worker ; -mno-odd-sp-reg doesn't need to affect double precision values so both cases 45*9880d681SAndroid Build Coastguard Worker ; use $f12 and $f13. 46*9880d681SAndroid Build Coastguard Worker 47*9880d681SAndroid Build Coastguard Worker %0 = fadd double %a, 1.0 48*9880d681SAndroid Build Coastguard Worker call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() 49*9880d681SAndroid Build Coastguard Worker %1 = fadd double %a, %0 50*9880d681SAndroid Build Coastguard Worker ret double %1 51*9880d681SAndroid Build Coastguard Worker} 52*9880d681SAndroid Build Coastguard Worker 53*9880d681SAndroid Build Coastguard Worker; ALL-LABEL: two_doubles: 54*9880d681SAndroid Build Coastguard Worker; ALL: add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}} 55*9880d681SAndroid Build Coastguard Worker; ALL: add.d $f0, $f12, $[[T0]] 56*9880d681SAndroid Build Coastguard Worker 57*9880d681SAndroid Build Coastguard Worker 58*9880d681SAndroid Build Coastguard Worker; INVALID: -mattr=+nooddspreg is not currently permitted for a 32-bit FPU register file (FR=0 mode). 59