xref: /aosp_15_r20/external/llvm/test/CodeGen/Mips/micromips-atomic.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58) 
1*9880d681SAndroid Build Coastguard Worker; RUN: llc %s -march=mipsel -mcpu=mips32r2 -mattr=micromips -filetype=asm \
2*9880d681SAndroid Build Coastguard Worker; RUN: -relocation-model=pic -o - | FileCheck %s
3*9880d681SAndroid Build Coastguard Worker
4*9880d681SAndroid Build Coastguard Worker@x = common global i32 0, align 4
5*9880d681SAndroid Build Coastguard Worker
6*9880d681SAndroid Build Coastguard Workerdefine i32 @AtomicLoadAdd32(i32 %incr) nounwind {
7*9880d681SAndroid Build Coastguard Workerentry:
8*9880d681SAndroid Build Coastguard Worker  %0 = atomicrmw add i32* @x, i32 %incr monotonic
9*9880d681SAndroid Build Coastguard Worker  ret i32 %0
10*9880d681SAndroid Build Coastguard Worker
11*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL:   AtomicLoadAdd32:
12*9880d681SAndroid Build Coastguard Worker; CHECK:   lw      $[[R0:[0-9]+]], %got(x)
13*9880d681SAndroid Build Coastguard Worker; CHECK:   $[[BB0:[A-Z_0-9]+]]:
14*9880d681SAndroid Build Coastguard Worker; CHECK:   ll      $[[R1:[0-9]+]], 0($[[R0]])
15*9880d681SAndroid Build Coastguard Worker; CHECK:   addu    $[[R2:[0-9]+]], $[[R1]], $4
16*9880d681SAndroid Build Coastguard Worker; CHECK:   sc      $[[R2]], 0($[[R0]])
17*9880d681SAndroid Build Coastguard Worker; CHECK:   beqzc   $[[R2]], $[[BB0]]
18*9880d681SAndroid Build Coastguard Worker}
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