1*9880d681SAndroid Build Coastguard Worker; Positive test for inline register constraints 2*9880d681SAndroid Build Coastguard Worker; 3*9880d681SAndroid Build Coastguard Worker; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s 4*9880d681SAndroid Build Coastguard Worker; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s 5*9880d681SAndroid Build Coastguard Worker 6*9880d681SAndroid Build Coastguard Workerdefine i32 @main() nounwind { 7*9880d681SAndroid Build Coastguard Workerentry: 8*9880d681SAndroid Build Coastguard Worker 9*9880d681SAndroid Build Coastguard Worker; r with char 10*9880d681SAndroid Build Coastguard Worker;CHECK: #APP 11*9880d681SAndroid Build Coastguard Worker;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23 12*9880d681SAndroid Build Coastguard Worker;CHECK: #NO_APP 13*9880d681SAndroid Build Coastguard Worker tail call i8 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i8 27, i8 23) nounwind 14*9880d681SAndroid Build Coastguard Worker 15*9880d681SAndroid Build Coastguard Worker; r with short 16*9880d681SAndroid Build Coastguard Worker;CHECK: #APP 17*9880d681SAndroid Build Coastguard Worker;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 13 18*9880d681SAndroid Build Coastguard Worker;CHECK: #NO_APP 19*9880d681SAndroid Build Coastguard Worker tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i16 17, i16 13) nounwind 20*9880d681SAndroid Build Coastguard Worker 21*9880d681SAndroid Build Coastguard Worker; r with int 22*9880d681SAndroid Build Coastguard Worker;CHECK: #APP 23*9880d681SAndroid Build Coastguard Worker;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3 24*9880d681SAndroid Build Coastguard Worker;CHECK: #NO_APP 25*9880d681SAndroid Build Coastguard Worker tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i32 7, i32 3) nounwind 26*9880d681SAndroid Build Coastguard Worker 27*9880d681SAndroid Build Coastguard Worker; Now c with 1024: make sure register $25 is picked 28*9880d681SAndroid Build Coastguard Worker; CHECK: #APP 29*9880d681SAndroid Build Coastguard Worker; CHECK: addiu $25, ${{[0-9]+}}, 1024 30*9880d681SAndroid Build Coastguard Worker; CHECK: #NO_APP 31*9880d681SAndroid Build Coastguard Worker tail call i32 asm sideeffect "addiu $0, $1, $2", "=c,c,I"(i32 4194304, i32 1024) nounwind 32*9880d681SAndroid Build Coastguard Worker 33*9880d681SAndroid Build Coastguard Worker; Now l with 1024: make sure register lo is picked. We do this by checking the instruction 34*9880d681SAndroid Build Coastguard Worker; after the inline expression for a mflo to pull the value out of lo. 35*9880d681SAndroid Build Coastguard Worker; CHECK: #APP 36*9880d681SAndroid Build Coastguard Worker; CHECK: mtlo ${{[0-9]+}} 37*9880d681SAndroid Build Coastguard Worker; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}} 38*9880d681SAndroid Build Coastguard Worker; CHECK: #NO_APP 39*9880d681SAndroid Build Coastguard Worker; CHECK-NEXT: mflo ${{[0-9]+}} 40*9880d681SAndroid Build Coastguard Worker %bosco = alloca i32, align 4 41*9880d681SAndroid Build Coastguard Worker call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind 42*9880d681SAndroid Build Coastguard Worker store volatile i32 %4, i32* %bosco, align 4 43*9880d681SAndroid Build Coastguard Worker 44*9880d681SAndroid Build Coastguard Worker ret i32 0 45*9880d681SAndroid Build Coastguard Worker} 46