1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; We have to XFAIL this temporarily because of the reversion of r229675. 3*9880d681SAndroid Build Coastguard Worker; XFAIL: * 4*9880d681SAndroid Build Coastguard Worker 5*9880d681SAndroid Build Coastguard Worker; Currently, the following IR assembly generates a KILL instruction between 6*9880d681SAndroid Build Coastguard Worker; the bitwise-and instruction and the return instruction. We verify that the 7*9880d681SAndroid Build Coastguard Worker; delay slot filler ignores such KILL instructions by filling the slot of the 8*9880d681SAndroid Build Coastguard Worker; return instruction properly. 9*9880d681SAndroid Build Coastguard Workerdefine signext i32 @f1(i32 signext %a, i32 signext %b) { 10*9880d681SAndroid Build Coastguard Workerentry: 11*9880d681SAndroid Build Coastguard Worker ; CHECK: jr $ra 12*9880d681SAndroid Build Coastguard Worker ; CHECK-NEXT: and $2, $4, $5 13*9880d681SAndroid Build Coastguard Worker 14*9880d681SAndroid Build Coastguard Worker %r = and i32 %a, %b 15*9880d681SAndroid Build Coastguard Worker ret i32 %r 16*9880d681SAndroid Build Coastguard Worker} 17