1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic 2*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic 3*9880d681SAndroid Build Coastguard Worker 4*9880d681SAndroid Build Coastguard Worker; The test is just to make sure it is able to allocate 5*9880d681SAndroid Build Coastguard Worker; registers for this example. There was an issue with allocating AC0 6*9880d681SAndroid Build Coastguard Worker; after a mul instruction. 7*9880d681SAndroid Build Coastguard Worker 8*9880d681SAndroid Build Coastguard Workerdeclare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) 9*9880d681SAndroid Build Coastguard Worker 10*9880d681SAndroid Build Coastguard Workerdefine i32 @foo(i32 %a, i32 %b) { 11*9880d681SAndroid Build Coastguard Workerentry: 12*9880d681SAndroid Build Coastguard Worker %0 = mul i32 %a, %b 13*9880d681SAndroid Build Coastguard Worker %1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %b) 14*9880d681SAndroid Build Coastguard Worker %2 = extractvalue { i32, i1 } %1, 0 15*9880d681SAndroid Build Coastguard Worker ret i32 %2 16*9880d681SAndroid Build Coastguard Worker} 17