1*9880d681SAndroid Build Coastguard Worker; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx < %s \ 2*9880d681SAndroid Build Coastguard Worker; RUN: | FileCheck %s 3*9880d681SAndroid Build Coastguard Worker 4*9880d681SAndroid Build Coastguard Worker; Check that the store to Q6VecPredResult does not get expanded into multiple 5*9880d681SAndroid Build Coastguard Worker; stores. There should be no memd's. This relies on the alignment specified 6*9880d681SAndroid Build Coastguard Worker; in the data layout string, so don't provide one here to make sure that the 7*9880d681SAndroid Build Coastguard Worker; default one from HexagonTargetMachine is correct. 8*9880d681SAndroid Build Coastguard Worker 9*9880d681SAndroid Build Coastguard Worker; CHECK-NOT: memd 10*9880d681SAndroid Build Coastguard Worker 11*9880d681SAndroid Build Coastguard Worker 12*9880d681SAndroid Build Coastguard Worker@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64 13*9880d681SAndroid Build Coastguard Worker 14*9880d681SAndroid Build Coastguard Worker; Function Attrs: nounwind 15*9880d681SAndroid Build Coastguard Workerdefine i32 @foo() #0 { 16*9880d681SAndroid Build Coastguard Workerentry: 17*9880d681SAndroid Build Coastguard Worker %0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 18*9880d681SAndroid Build Coastguard Worker %1 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %0, i32 -2147483648) 19*9880d681SAndroid Build Coastguard Worker store <512 x i1> %1, <512 x i1>* bitcast (<16 x i32>* @Q6VecPredResult to <512 x i1>*), align 64, !tbaa !1 20*9880d681SAndroid Build Coastguard Worker tail call void @print_vecpred(i32 64, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3 21*9880d681SAndroid Build Coastguard Worker ret i32 0 22*9880d681SAndroid Build Coastguard Worker} 23*9880d681SAndroid Build Coastguard Worker 24*9880d681SAndroid Build Coastguard Worker; Function Attrs: nounwind readnone 25*9880d681SAndroid Build Coastguard Workerdeclare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1 26*9880d681SAndroid Build Coastguard Worker 27*9880d681SAndroid Build Coastguard Worker; Function Attrs: nounwind readnone 28*9880d681SAndroid Build Coastguard Workerdeclare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 29*9880d681SAndroid Build Coastguard Worker 30*9880d681SAndroid Build Coastguard Workerdeclare void @print_vecpred(i32, i8*) #2 31*9880d681SAndroid Build Coastguard Worker 32*9880d681SAndroid Build Coastguard Workerattributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } 33*9880d681SAndroid Build Coastguard Workerattributes #1 = { nounwind readnone } 34*9880d681SAndroid Build Coastguard Workerattributes #2 = { nounwind } 35*9880d681SAndroid Build Coastguard Worker 36*9880d681SAndroid Build Coastguard Worker!1 = !{!2, !2, i64 0} 37*9880d681SAndroid Build Coastguard Worker!2 = !{!"omnipotent char", !3, i64 0} 38*9880d681SAndroid Build Coastguard Worker!3 = !{!"Simple C/C++ TBAA"} 39