1*9880d681SAndroid Build Coastguard Worker; RUN: llc -O2 -mcpu=hexagonv5 < %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; There should be no register pair used. 3*9880d681SAndroid Build Coastguard Worker; CHECK-NOT: r{{.*}}:{{[0-9]}} = and 4*9880d681SAndroid Build Coastguard Worker; CHECK-NOT: r{{.*}}:{{[0-9]}} = xor 5*9880d681SAndroid Build Coastguard Workertarget datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" 6*9880d681SAndroid Build Coastguard Workertarget triple = "hexagon" 7*9880d681SAndroid Build Coastguard Worker 8*9880d681SAndroid Build Coastguard Workerdefine i32 @foo(i64 %x, i64 %y, i64 %z) nounwind readnone { 9*9880d681SAndroid Build Coastguard Workerentry: 10*9880d681SAndroid Build Coastguard Worker %and = and i64 %y, -361700868401135616 11*9880d681SAndroid Build Coastguard Worker %xor = xor i64 %and, %z 12*9880d681SAndroid Build Coastguard Worker %shr1 = lshr i64 %xor, 32 13*9880d681SAndroid Build Coastguard Worker %conv = trunc i64 %shr1 to i32 14*9880d681SAndroid Build Coastguard Worker ret i32 %conv 15*9880d681SAndroid Build Coastguard Worker} 16