1*9880d681SAndroid Build Coastguard Worker; RUN: llc -march=hexagon -hexagon-extract=0 < %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; Check that we generate fused logical and with shift instruction. 3*9880d681SAndroid Build Coastguard Worker; Disable "extract" generation, since it may eliminate the and/lsr. 4*9880d681SAndroid Build Coastguard Worker 5*9880d681SAndroid Build Coastguard Worker; CHECK: r{{[0-9]+}} = and(#15, lsr(r{{[0-9]+}}, #{{[0-9]+}}) 6*9880d681SAndroid Build Coastguard Worker 7*9880d681SAndroid Build Coastguard Workerdefine i32 @main(i16* %a, i16* %b) nounwind { 8*9880d681SAndroid Build Coastguard Worker entry: 9*9880d681SAndroid Build Coastguard Worker %0 = load i16, i16* %a, align 2 10*9880d681SAndroid Build Coastguard Worker %conv1 = sext i16 %0 to i32 11*9880d681SAndroid Build Coastguard Worker %shr1 = ashr i32 %conv1, 3 12*9880d681SAndroid Build Coastguard Worker %and1 = and i32 %shr1, 15 13*9880d681SAndroid Build Coastguard Worker %conv2 = trunc i32 %and1 to i16 14*9880d681SAndroid Build Coastguard Worker store i16 %conv2, i16* %b, align 2 15*9880d681SAndroid Build Coastguard Worker ret i32 0 16*9880d681SAndroid Build Coastguard Worker} 17*9880d681SAndroid Build Coastguard Worker 18