1*9880d681SAndroid Build Coastguard Worker; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; Check that we generate conversion from single precision floating point 3*9880d681SAndroid Build Coastguard Worker; to 64-bit int value in IEEE complaint mode in V5. 4*9880d681SAndroid Build Coastguard Worker 5*9880d681SAndroid Build Coastguard Worker; CHECK: r{{[0-9]+}}:{{[0-9]+}} = convert_sf2d(r{{[0-9]+}}) 6*9880d681SAndroid Build Coastguard Worker 7*9880d681SAndroid Build Coastguard Workerdefine i32 @main() nounwind { 8*9880d681SAndroid Build Coastguard Workerentry: 9*9880d681SAndroid Build Coastguard Worker %retval = alloca i32, align 4 10*9880d681SAndroid Build Coastguard Worker %i = alloca i64, align 8 11*9880d681SAndroid Build Coastguard Worker %a = alloca float, align 4 12*9880d681SAndroid Build Coastguard Worker %b = alloca float, align 4 13*9880d681SAndroid Build Coastguard Worker %c = alloca float, align 4 14*9880d681SAndroid Build Coastguard Worker store i32 0, i32* %retval 15*9880d681SAndroid Build Coastguard Worker store float 0x402ECCCCC0000000, float* %a, align 4 16*9880d681SAndroid Build Coastguard Worker store float 0x4022333340000000, float* %b, align 4 17*9880d681SAndroid Build Coastguard Worker %0 = load float, float* %a, align 4 18*9880d681SAndroid Build Coastguard Worker %1 = load float, float* %b, align 4 19*9880d681SAndroid Build Coastguard Worker %add = fadd float %0, %1 20*9880d681SAndroid Build Coastguard Worker store float %add, float* %c, align 4 21*9880d681SAndroid Build Coastguard Worker %2 = load float, float* %c, align 4 22*9880d681SAndroid Build Coastguard Worker %conv = fptosi float %2 to i64 23*9880d681SAndroid Build Coastguard Worker store i64 %conv, i64* %i, align 8 24*9880d681SAndroid Build Coastguard Worker %3 = load i64, i64* %i, align 8 25*9880d681SAndroid Build Coastguard Worker %conv1 = trunc i64 %3 to i32 26*9880d681SAndroid Build Coastguard Worker ret i32 %conv1 27*9880d681SAndroid Build Coastguard Worker} 28