1*9880d681SAndroid Build Coastguard Worker; RUN: llc -mtriple=armv7-apple-ios6.0 -mcpu=swift < %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; RUN: llc -mtriple=armv7-apple-ios6.0 < %s | FileCheck %s --check-prefix=CHECK-STRICT-ATOMIC 3*9880d681SAndroid Build Coastguard Worker 4*9880d681SAndroid Build Coastguard Worker; Release operations only need the store barrier provided by a "dmb ishst", 5*9880d681SAndroid Build Coastguard Worker 6*9880d681SAndroid Build Coastguard Workerdefine void @test_store_release(i32* %p, i32 %v) { 7*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: test_store_release: 8*9880d681SAndroid Build Coastguard Worker; CHECK: dmb ishst 9*9880d681SAndroid Build Coastguard Worker; CHECK: str 10*9880d681SAndroid Build Coastguard Worker 11*9880d681SAndroid Build Coastguard Worker; CHECK-STRICT-ATOMIC-LABEL: test_store_release: 12*9880d681SAndroid Build Coastguard Worker; CHECK-STRICT-ATOMIC: dmb {{ish$}} 13*9880d681SAndroid Build Coastguard Worker store atomic i32 %v, i32* %p release, align 4 14*9880d681SAndroid Build Coastguard Worker ret void 15*9880d681SAndroid Build Coastguard Worker} 16*9880d681SAndroid Build Coastguard Worker 17*9880d681SAndroid Build Coastguard Worker; However, if sequential consistency is needed *something* must ensure a release 18*9880d681SAndroid Build Coastguard Worker; followed by an acquire does not get reordered. In that case a "dmb ishst" is 19*9880d681SAndroid Build Coastguard Worker; not adequate. 20*9880d681SAndroid Build Coastguard Workerdefine i32 @test_seq_cst(i32* %p, i32 %v) { 21*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: test_seq_cst: 22*9880d681SAndroid Build Coastguard Worker; CHECK: dmb ishst 23*9880d681SAndroid Build Coastguard Worker; CHECK: str 24*9880d681SAndroid Build Coastguard Worker; CHECK: dmb {{ish$}} 25*9880d681SAndroid Build Coastguard Worker; CHECK: ldr 26*9880d681SAndroid Build Coastguard Worker; CHECK: dmb {{ish$}} 27*9880d681SAndroid Build Coastguard Worker 28*9880d681SAndroid Build Coastguard Worker; CHECK-STRICT-ATOMIC-LABEL: test_seq_cst: 29*9880d681SAndroid Build Coastguard Worker; CHECK-STRICT-ATOMIC: dmb {{ish$}} 30*9880d681SAndroid Build Coastguard Worker; CHECK-STRICT-ATOMIC: str 31*9880d681SAndroid Build Coastguard Worker; CHECK-STRICT-ATOMIC: dmb {{ish$}} 32*9880d681SAndroid Build Coastguard Worker; CHECK-STRICT-ATOMIC: ldr 33*9880d681SAndroid Build Coastguard Worker; CHECK-STRICT-ATOMIC: dmb {{ish$}} 34*9880d681SAndroid Build Coastguard Worker 35*9880d681SAndroid Build Coastguard Worker store atomic i32 %v, i32* %p seq_cst, align 4 36*9880d681SAndroid Build Coastguard Worker %val = load atomic i32, i32* %p seq_cst, align 4 37*9880d681SAndroid Build Coastguard Worker ret i32 %val 38*9880d681SAndroid Build Coastguard Worker} 39*9880d681SAndroid Build Coastguard Worker 40*9880d681SAndroid Build Coastguard Worker; Also, pure acquire operations should definitely not have an ishst barrier. 41*9880d681SAndroid Build Coastguard Worker 42*9880d681SAndroid Build Coastguard Workerdefine i32 @test_acq(i32* %addr) { 43*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: test_acq: 44*9880d681SAndroid Build Coastguard Worker; CHECK: ldr 45*9880d681SAndroid Build Coastguard Worker; CHECK: dmb {{ish$}} 46*9880d681SAndroid Build Coastguard Worker 47*9880d681SAndroid Build Coastguard Worker; CHECK-STRICT-ATOMIC-LABEL: test_acq: 48*9880d681SAndroid Build Coastguard Worker; CHECK-STRICT-ATOMIC: dmb {{ish$}} 49*9880d681SAndroid Build Coastguard Worker %val = load atomic i32, i32* %addr acquire, align 4 50*9880d681SAndroid Build Coastguard Worker ret i32 %val 51*9880d681SAndroid Build Coastguard Worker} 52