xref: /aosp_15_r20/external/llvm/test/CodeGen/ARM/gpr-paired-spill.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58)
1*9880d681SAndroid Build Coastguard Worker; RUN: llc -mtriple=armv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITH-LDRD
2*9880d681SAndroid Build Coastguard Worker; RUN: llc -mtriple=armv4-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITHOUT-LDRD
3*9880d681SAndroid Build Coastguard Worker; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITH-LDRD
4*9880d681SAndroid Build Coastguard Worker
5*9880d681SAndroid Build Coastguard Workerdefine void @foo(i64* %addr) {
6*9880d681SAndroid Build Coastguard Worker  %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
7*9880d681SAndroid Build Coastguard Worker  %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
8*9880d681SAndroid Build Coastguard Worker  %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
9*9880d681SAndroid Build Coastguard Worker  %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
10*9880d681SAndroid Build Coastguard Worker  %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
11*9880d681SAndroid Build Coastguard Worker  %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
12*9880d681SAndroid Build Coastguard Worker  %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
13*9880d681SAndroid Build Coastguard Worker
14*9880d681SAndroid Build Coastguard Worker  ; Key point is that enough 64-bit paired GPR values are live that
15*9880d681SAndroid Build Coastguard Worker  ; one of them has to be spilled. This used to cause an abort because
16*9880d681SAndroid Build Coastguard Worker  ; an LDMIA was created with both a FrameIndex and an offset, which
17*9880d681SAndroid Build Coastguard Worker  ; is not allowed.
18*9880d681SAndroid Build Coastguard Worker
19*9880d681SAndroid Build Coastguard Worker; CHECK-WITH-LDRD: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]
20*9880d681SAndroid Build Coastguard Worker; CHECK-WITH-LDRD: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp]
21*9880d681SAndroid Build Coastguard Worker
22*9880d681SAndroid Build Coastguard Worker; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]
23*9880d681SAndroid Build Coastguard Worker; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp]
24*9880d681SAndroid Build Coastguard Worker
25*9880d681SAndroid Build Coastguard Worker  ; We also want to ensure the register scavenger is working (i.e. an
26*9880d681SAndroid Build Coastguard Worker  ; offset from sp can be generated), so we need two spills.
27*9880d681SAndroid Build Coastguard Worker; CHECK-WITHOUT-LDRD: add [[ADDRREG:[a-z0-9]+]], sp, #{{[0-9]+}}
28*9880d681SAndroid Build Coastguard Worker; CHECK-WITHOUT-LDRD: stm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
29*9880d681SAndroid Build Coastguard Worker; CHECK-WITHOUT-LDRD: stm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
30*9880d681SAndroid Build Coastguard Worker
31*9880d681SAndroid Build Coastguard Worker  ; In principle LLVM may have to recalculate the offset. At the moment
32*9880d681SAndroid Build Coastguard Worker  ; it reuses the original though.
33*9880d681SAndroid Build Coastguard Worker; CHECK-WITHOUT-LDRD: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
34*9880d681SAndroid Build Coastguard Worker; CHECK-WITHOUT-LDRD: ldm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
35*9880d681SAndroid Build Coastguard Worker
36*9880d681SAndroid Build Coastguard Worker  store volatile i64 %val1, i64* %addr
37*9880d681SAndroid Build Coastguard Worker  store volatile i64 %val2, i64* %addr
38*9880d681SAndroid Build Coastguard Worker  store volatile i64 %val3, i64* %addr
39*9880d681SAndroid Build Coastguard Worker  store volatile i64 %val4, i64* %addr
40*9880d681SAndroid Build Coastguard Worker  store volatile i64 %val5, i64* %addr
41*9880d681SAndroid Build Coastguard Worker  store volatile i64 %val6, i64* %addr
42*9880d681SAndroid Build Coastguard Worker  store volatile i64 %val7, i64* %addr
43*9880d681SAndroid Build Coastguard Worker  ret void
44*9880d681SAndroid Build Coastguard Worker}
45