1*9880d681SAndroid Build Coastguard Worker; RUN: llc -O0 -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker 3*9880d681SAndroid Build Coastguard Workerdeclare arm_aapcs_vfpcc i32 @num_entries() 4*9880d681SAndroid Build Coastguard Worker 5*9880d681SAndroid Build Coastguard Workerdefine arm_aapcs_vfpcc void @test___builtin_alloca() { 6*9880d681SAndroid Build Coastguard Workerentry: 7*9880d681SAndroid Build Coastguard Worker %array = alloca i8*, align 4 8*9880d681SAndroid Build Coastguard Worker %call = call arm_aapcs_vfpcc i32 @num_entries() 9*9880d681SAndroid Build Coastguard Worker %mul = mul i32 4, %call 10*9880d681SAndroid Build Coastguard Worker %0 = alloca i8, i32 %mul 11*9880d681SAndroid Build Coastguard Worker store i8* %0, i8** %array, align 4 12*9880d681SAndroid Build Coastguard Worker ret void 13*9880d681SAndroid Build Coastguard Worker} 14*9880d681SAndroid Build Coastguard Worker 15*9880d681SAndroid Build Coastguard Worker; CHECK: bl num_entries 16*9880d681SAndroid Build Coastguard Worker; Any register is actually valid here, but turns out we use lr, 17*9880d681SAndroid Build Coastguard Worker; because we do not have the kill flag on R0. 18*9880d681SAndroid Build Coastguard Worker; CHECK: mov.w [[R1:lr]], #7 19*9880d681SAndroid Build Coastguard Worker; CHECK: add.w [[R0:r[0-9]+]], [[R1]], [[R0]], lsl #2 20*9880d681SAndroid Build Coastguard Worker; CHECK: bic [[R0]], [[R0]], #7 21*9880d681SAndroid Build Coastguard Worker; CHECK: lsrs r4, [[R0]], #2 22*9880d681SAndroid Build Coastguard Worker; CHECK: bl __chkstk 23*9880d681SAndroid Build Coastguard Worker; CHECK: sub.w sp, sp, r4 24*9880d681SAndroid Build Coastguard Worker 25