1*9880d681SAndroid Build Coastguard Worker;PR14492 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA 2*9880d681SAndroid Build Coastguard Worker;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s 3*9880d681SAndroid Build Coastguard Worker;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s 4*9880d681SAndroid Build Coastguard Worker 5*9880d681SAndroid Build Coastguard Worker;EXPECTED-LABEL: foo: 6*9880d681SAndroid Build Coastguard Worker;CHECK-LABEL: foo: 7*9880d681SAndroid Build Coastguard Workerdefine i32 @foo(i32* %a) nounwind optsize { 8*9880d681SAndroid Build Coastguard Workerentry: 9*9880d681SAndroid Build Coastguard Worker %0 = load i32, i32* %a, align 4 10*9880d681SAndroid Build Coastguard Worker %arrayidx1 = getelementptr inbounds i32, i32* %a, i32 1 11*9880d681SAndroid Build Coastguard Worker %1 = load i32, i32* %arrayidx1, align 4 12*9880d681SAndroid Build Coastguard Worker %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 2 13*9880d681SAndroid Build Coastguard Worker %2 = load i32, i32* %arrayidx2, align 4 14*9880d681SAndroid Build Coastguard Worker %add.ptr = getelementptr inbounds i32, i32* %a, i32 3 15*9880d681SAndroid Build Coastguard Worker;Make sure we do not have a duplicated register in the front of the reg list 16*9880d681SAndroid Build Coastguard Worker;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}}, 17*9880d681SAndroid Build Coastguard Worker;CHECK-NOT: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], [[REG]], 18*9880d681SAndroid Build Coastguard Worker tail call void @bar(i32* %add.ptr) nounwind optsize 19*9880d681SAndroid Build Coastguard Worker %add = add nsw i32 %1, %0 20*9880d681SAndroid Build Coastguard Worker %add3 = add nsw i32 %add, %2 21*9880d681SAndroid Build Coastguard Worker ret i32 %add3 22*9880d681SAndroid Build Coastguard Worker} 23*9880d681SAndroid Build Coastguard Worker 24*9880d681SAndroid Build Coastguard Workerdeclare void @bar(i32*) optsize 25