1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s 2*9880d681SAndroid Build Coastguard Workertarget datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" 3*9880d681SAndroid Build Coastguard Workertarget triple = "thumbv7-apple-darwin10" 4*9880d681SAndroid Build Coastguard Worker 5*9880d681SAndroid Build Coastguard Worker; This tests the fast register allocator's handling of partial redefines: 6*9880d681SAndroid Build Coastguard Worker; 7*9880d681SAndroid Build Coastguard Worker; %reg1028:dsub_0<def>, %reg1028:dsub_1<def> = VLD1q64 %reg1025... 8*9880d681SAndroid Build Coastguard Worker; %reg1030:dsub_1<def> = COPY %reg1028:dsub_0<kill> 9*9880d681SAndroid Build Coastguard Worker; 10*9880d681SAndroid Build Coastguard Worker; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial 11*9880d681SAndroid Build Coastguard Worker; redef, it cannot also get %Q0. 12*9880d681SAndroid Build Coastguard Worker 13*9880d681SAndroid Build Coastguard Worker; CHECK: vld1.64 {d16, d17}, [r{{.}}] 14*9880d681SAndroid Build Coastguard Worker; CHECK-NOT: vld1.64 {d16, d17} 15*9880d681SAndroid Build Coastguard Worker; CHECK: vmov.f64 16*9880d681SAndroid Build Coastguard Worker 17*9880d681SAndroid Build Coastguard Workerdefine i32 @test(i8* %arg) nounwind { 18*9880d681SAndroid Build Coastguard Workerentry: 19*9880d681SAndroid Build Coastguard Worker %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* %arg, i32 1) 20*9880d681SAndroid Build Coastguard Worker %1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2> 21*9880d681SAndroid Build Coastguard Worker store <2 x i64> %1, <2 x i64>* undef, align 16 22*9880d681SAndroid Build Coastguard Worker ret i32 undef 23*9880d681SAndroid Build Coastguard Worker} 24*9880d681SAndroid Build Coastguard Worker 25*9880d681SAndroid Build Coastguard Workerdeclare <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8*, i32) nounwind readonly 26