xref: /aosp_15_r20/external/llvm/test/CodeGen/AMDGPU/store-v3i32.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58)
1*9880d681SAndroid Build Coastguard Worker; XFAIL: *
2*9880d681SAndroid Build Coastguard Worker; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI %s
3*9880d681SAndroid Build Coastguard Worker; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s
4*9880d681SAndroid Build Coastguard Worker
5*9880d681SAndroid Build Coastguard Worker; 3 vectors have the same size and alignment as 4 vectors, so this
6*9880d681SAndroid Build Coastguard Worker; should be done in a single store.
7*9880d681SAndroid Build Coastguard Worker
8*9880d681SAndroid Build Coastguard Worker; SI-LABEL: {{^}}store_v3i32:
9*9880d681SAndroid Build Coastguard Worker; SI: buffer_store_dwordx4
10*9880d681SAndroid Build Coastguard Workerdefine void @store_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a) nounwind {
11*9880d681SAndroid Build Coastguard Worker  store <3 x i32> %a, <3 x i32> addrspace(1)* %out, align 16
12*9880d681SAndroid Build Coastguard Worker  ret void
13*9880d681SAndroid Build Coastguard Worker}
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