1*9880d681SAndroid Build Coastguard Worker;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker 3*9880d681SAndroid Build Coastguard Worker;CHECK-LABEL: test1: 4*9880d681SAndroid Build Coastguard Worker;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 5*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, 6*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, 7*9880d681SAndroid Build Coastguard Worker 8*9880d681SAndroid Build Coastguard Workerdefine amdgpu_ps void @test1(<4 x float> inreg %reg0) { 9*9880d681SAndroid Build Coastguard Worker %r0 = extractelement <4 x float> %reg0, i32 0 10*9880d681SAndroid Build Coastguard Worker %r1 = extractelement <4 x float> %reg0, i32 1 11*9880d681SAndroid Build Coastguard Worker %r2 = call float @llvm.pow.f32( float %r0, float %r1) 12*9880d681SAndroid Build Coastguard Worker %vec = insertelement <4 x float> undef, float %r2, i32 0 13*9880d681SAndroid Build Coastguard Worker call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) 14*9880d681SAndroid Build Coastguard Worker ret void 15*9880d681SAndroid Build Coastguard Worker} 16*9880d681SAndroid Build Coastguard Worker 17*9880d681SAndroid Build Coastguard Worker;CHECK-LABEL: test2: 18*9880d681SAndroid Build Coastguard Worker;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 19*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, 20*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 21*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, 22*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, 23*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, 24*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 25*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, 26*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 27*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, 28*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, 29*9880d681SAndroid Build Coastguard Worker;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, 30*9880d681SAndroid Build Coastguard Workerdefine amdgpu_ps void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { 31*9880d681SAndroid Build Coastguard Worker %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1) 32*9880d681SAndroid Build Coastguard Worker call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) 33*9880d681SAndroid Build Coastguard Worker ret void 34*9880d681SAndroid Build Coastguard Worker} 35*9880d681SAndroid Build Coastguard Worker 36*9880d681SAndroid Build Coastguard Workerdeclare float @llvm.pow.f32(float ,float ) readonly 37*9880d681SAndroid Build Coastguard Workerdeclare <4 x float> @llvm.pow.v4f32(<4 x float> ,<4 x float> ) readonly 38*9880d681SAndroid Build Coastguard Workerdeclare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) 39