1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3*9880d681SAndroid Build Coastguard Worker 4*9880d681SAndroid Build Coastguard Workertarget triple = "amdgcn--" 5*9880d681SAndroid Build Coastguard Worker 6*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: {{^}}main: 7*9880d681SAndroid Build Coastguard Worker; 8*9880d681SAndroid Build Coastguard Worker; Test for compilation only. This generated an invalid machine instruction 9*9880d681SAndroid Build Coastguard Worker; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both 10*9880d681SAndroid Build Coastguard Worker; of which were in SGPRs. 11*9880d681SAndroid Build Coastguard Workerdefine amdgpu_vs float @main(i32 %v) { 12*9880d681SAndroid Build Coastguard Workermain_body: 13*9880d681SAndroid Build Coastguard Worker %d1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 960) 14*9880d681SAndroid Build Coastguard Worker %d2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 976) 15*9880d681SAndroid Build Coastguard Worker br i1 undef, label %ENDIF56, label %IF57 16*9880d681SAndroid Build Coastguard Worker 17*9880d681SAndroid Build Coastguard WorkerIF57: ; preds = %ENDIF 18*9880d681SAndroid Build Coastguard Worker %v.1 = mul i32 %v, 2 19*9880d681SAndroid Build Coastguard Worker br label %ENDIF56 20*9880d681SAndroid Build Coastguard Worker 21*9880d681SAndroid Build Coastguard WorkerENDIF56: ; preds = %IF57, %ENDIF 22*9880d681SAndroid Build Coastguard Worker %v.2 = phi i32 [ %v, %main_body ], [ %v.1, %IF57 ] 23*9880d681SAndroid Build Coastguard Worker %d1.i = bitcast float %d1 to i32 24*9880d681SAndroid Build Coastguard Worker %cc1 = icmp eq i32 %d1.i, 0 25*9880d681SAndroid Build Coastguard Worker br i1 %cc1, label %ENDIF59, label %IF60 26*9880d681SAndroid Build Coastguard Worker 27*9880d681SAndroid Build Coastguard WorkerIF60: ; preds = %ENDIF56 28*9880d681SAndroid Build Coastguard Worker %v.3 = mul i32 %v.2, 2 29*9880d681SAndroid Build Coastguard Worker br label %ENDIF59 30*9880d681SAndroid Build Coastguard Worker 31*9880d681SAndroid Build Coastguard WorkerENDIF59: ; preds = %IF60, %ENDIF56 32*9880d681SAndroid Build Coastguard Worker %v.4 = phi i32 [ %v.2, %ENDIF56 ], [ %v.3, %IF60 ] 33*9880d681SAndroid Build Coastguard Worker %d2.i = bitcast float %d2 to i32 34*9880d681SAndroid Build Coastguard Worker %cc2 = icmp eq i32 %d2.i, 0 35*9880d681SAndroid Build Coastguard Worker br i1 %cc2, label %ENDIF62, label %IF63 36*9880d681SAndroid Build Coastguard Worker 37*9880d681SAndroid Build Coastguard WorkerIF63: ; preds = %ENDIF59 38*9880d681SAndroid Build Coastguard Worker unreachable 39*9880d681SAndroid Build Coastguard Worker 40*9880d681SAndroid Build Coastguard WorkerENDIF62: ; preds = %ENDIF59 41*9880d681SAndroid Build Coastguard Worker %r = bitcast i32 %v.4 to float 42*9880d681SAndroid Build Coastguard Worker ret float %r 43*9880d681SAndroid Build Coastguard Worker} 44*9880d681SAndroid Build Coastguard Worker 45*9880d681SAndroid Build Coastguard Worker; Function Attrs: nounwind readnone 46*9880d681SAndroid Build Coastguard Workerdeclare float @llvm.SI.load.const(<16 x i8>, i32) #0 47*9880d681SAndroid Build Coastguard Worker 48*9880d681SAndroid Build Coastguard Workerattributes #0 = { nounwind readnone } 49*9880d681SAndroid Build Coastguard Workerattributes #1 = { readnone } 50