1*9880d681SAndroid Build Coastguard Worker; REQUIRES: asserts 2*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s 3*9880d681SAndroid Build Coastguard Worker; 4*9880d681SAndroid Build Coastguard Worker; For Cortex-A53, shiftable operands that are not actually shifted 5*9880d681SAndroid Build Coastguard Worker; are not needed for an additional two cycles. 6*9880d681SAndroid Build Coastguard Worker; 7*9880d681SAndroid Build Coastguard Worker; CHECK: ********** MI Scheduling ********** 8*9880d681SAndroid Build Coastguard Worker; CHECK: shiftable 9*9880d681SAndroid Build Coastguard Worker; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0 10*9880d681SAndroid Build Coastguard Worker; CHECK: Successors: 11*9880d681SAndroid Build Coastguard Worker; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2 12*9880d681SAndroid Build Coastguard Worker; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2 13*9880d681SAndroid Build Coastguard Worker; CHECK: ********** INTERVALS ********** 14*9880d681SAndroid Build Coastguard Workerdefine i64 @shiftable(i64 %A, i64 %B) { 15*9880d681SAndroid Build Coastguard Worker %tmp0 = sub i64 %B, 20 16*9880d681SAndroid Build Coastguard Worker %tmp1 = shl i64 %tmp0, 5; 17*9880d681SAndroid Build Coastguard Worker %tmp2 = add i64 %A, %tmp1; 18*9880d681SAndroid Build Coastguard Worker %tmp3 = add i64 %A, %tmp0 19*9880d681SAndroid Build Coastguard Worker %tmp4 = mul i64 %tmp2, %tmp3 20*9880d681SAndroid Build Coastguard Worker 21*9880d681SAndroid Build Coastguard Worker ret i64 %tmp4 22*9880d681SAndroid Build Coastguard Worker} 23