1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker 3*9880d681SAndroid Build Coastguard Workertarget datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" 4*9880d681SAndroid Build Coastguard Workertarget triple = "aarch64-unknown-linux-gnu" 5*9880d681SAndroid Build Coastguard Worker 6*9880d681SAndroid Build Coastguard Workerdefine <4 x i16> @f(<4 x i32> %vqdmlal_v3.i, <8 x i16> %x5) { 7*9880d681SAndroid Build Coastguard Workerentry: 8*9880d681SAndroid Build Coastguard Worker ; Check that we don't just dup the input vector. The code emitted is ext, dup, ext, ext 9*9880d681SAndroid Build Coastguard Worker ; but only match the last three instructions as the first two could be combined to 10*9880d681SAndroid Build Coastguard Worker ; a dup2 at some stage. 11*9880d681SAndroid Build Coastguard Worker ; CHECK: dup 12*9880d681SAndroid Build Coastguard Worker ; CHECK: ext 13*9880d681SAndroid Build Coastguard Worker ; CHECK: ext 14*9880d681SAndroid Build Coastguard Worker %x4 = extractelement <4 x i32> %vqdmlal_v3.i, i32 2 15*9880d681SAndroid Build Coastguard Worker %vgetq_lane = trunc i32 %x4 to i16 16*9880d681SAndroid Build Coastguard Worker %vecinit.i = insertelement <4 x i16> undef, i16 %vgetq_lane, i32 0 17*9880d681SAndroid Build Coastguard Worker %vecinit2.i = insertelement <4 x i16> %vecinit.i, i16 %vgetq_lane, i32 2 18*9880d681SAndroid Build Coastguard Worker %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vgetq_lane, i32 3 19*9880d681SAndroid Build Coastguard Worker %vgetq_lane261 = extractelement <8 x i16> %x5, i32 0 20*9880d681SAndroid Build Coastguard Worker %vset_lane267 = insertelement <4 x i16> %vecinit3.i, i16 %vgetq_lane261, i32 1 21*9880d681SAndroid Build Coastguard Worker ret <4 x i16> %vset_lane267 22*9880d681SAndroid Build Coastguard Worker} 23