1*9880d681SAndroid Build Coastguard Worker//===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===// 2*9880d681SAndroid Build Coastguard Worker// 3*9880d681SAndroid Build Coastguard Worker// The LLVM Compiler Infrastructure 4*9880d681SAndroid Build Coastguard Worker// 5*9880d681SAndroid Build Coastguard Worker// This file is distributed under the University of Illinois Open Source 6*9880d681SAndroid Build Coastguard Worker// License. See LICENSE.TXT for details. 7*9880d681SAndroid Build Coastguard Worker// 8*9880d681SAndroid Build Coastguard Worker//===----------------------------------------------------------------------===// 9*9880d681SAndroid Build Coastguard Worker// 10*9880d681SAndroid Build Coastguard Worker// Tablegen register definitions common to all hw codegen targets. 11*9880d681SAndroid Build Coastguard Worker// 12*9880d681SAndroid Build Coastguard Worker//===----------------------------------------------------------------------===// 13*9880d681SAndroid Build Coastguard Worker 14*9880d681SAndroid Build Coastguard Workerlet Namespace = "AMDGPU" in { 15*9880d681SAndroid Build Coastguard Worker 16*9880d681SAndroid Build Coastguard Workerforeach Index = 0-15 in { 17*9880d681SAndroid Build Coastguard Worker def sub#Index : SubRegIndex<32, !shl(Index, 5)>; 18*9880d681SAndroid Build Coastguard Worker} 19*9880d681SAndroid Build Coastguard Worker 20*9880d681SAndroid Build Coastguard Workerdef INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">; 21*9880d681SAndroid Build Coastguard Worker 22*9880d681SAndroid Build Coastguard Worker} 23*9880d681SAndroid Build Coastguard Worker 24*9880d681SAndroid Build Coastguard Workerinclude "R600RegisterInfo.td" 25*9880d681SAndroid Build Coastguard Workerinclude "SIRegisterInfo.td" 26