xref: /aosp_15_r20/external/libhevc/encoder/rate_control_api_structs.h (revision c83a76b084498d55f252f48b2e3786804cdf24b7)
1*c83a76b0SSuyog Pawar /******************************************************************************
2*c83a76b0SSuyog Pawar  *
3*c83a76b0SSuyog Pawar  * Copyright (C) 2018 The Android Open Source Project
4*c83a76b0SSuyog Pawar  *
5*c83a76b0SSuyog Pawar  * Licensed under the Apache License, Version 2.0 (the "License");
6*c83a76b0SSuyog Pawar  * you may not use this file except in compliance with the License.
7*c83a76b0SSuyog Pawar  * You may obtain a copy of the License at:
8*c83a76b0SSuyog Pawar  *
9*c83a76b0SSuyog Pawar  * http://www.apache.org/licenses/LICENSE-2.0
10*c83a76b0SSuyog Pawar  *
11*c83a76b0SSuyog Pawar  * Unless required by applicable law or agreed to in writing, software
12*c83a76b0SSuyog Pawar  * distributed under the License is distributed on an "AS IS" BASIS,
13*c83a76b0SSuyog Pawar  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14*c83a76b0SSuyog Pawar  * See the License for the specific language governing permissions and
15*c83a76b0SSuyog Pawar  * limitations under the License.
16*c83a76b0SSuyog Pawar  *
17*c83a76b0SSuyog Pawar  *****************************************************************************
18*c83a76b0SSuyog Pawar  * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19*c83a76b0SSuyog Pawar */
20*c83a76b0SSuyog Pawar /*!
21*c83a76b0SSuyog Pawar ******************************************************************************
22*c83a76b0SSuyog Pawar * \file rate_control_api_structs.h
23*c83a76b0SSuyog Pawar *
24*c83a76b0SSuyog Pawar * \brief
25*c83a76b0SSuyog Pawar *    This file contains rate_control API struct and constant macro
26*c83a76b0SSuyog Pawar *
27*c83a76b0SSuyog Pawar * \date
28*c83a76b0SSuyog Pawar *
29*c83a76b0SSuyog Pawar * \author
30*c83a76b0SSuyog Pawar *    ittiam
31*c83a76b0SSuyog Pawar *
32*c83a76b0SSuyog Pawar ******************************************************************************
33*c83a76b0SSuyog Pawar */
34*c83a76b0SSuyog Pawar #ifndef _RATE_CONTROL_API_STRUCTS_H_
35*c83a76b0SSuyog Pawar #define _RATE_CONTROL_API_STRUCTS_H_
36*c83a76b0SSuyog Pawar 
37*c83a76b0SSuyog Pawar /* The following definitions were present in rc_cntrl_param.h, moved to this file
38*c83a76b0SSuyog Pawar    as it is used by rate_control_api.c*/
39*c83a76b0SSuyog Pawar /*#define VBR_BIT_ALLOC_PERIOD 3  num_frm_in_period = BIT_ALLOC_PERIOD*intra_frame_interval */
40*c83a76b0SSuyog Pawar /*****************************************************************************/
41*c83a76b0SSuyog Pawar /* Constant Macros                                                           */
42*c83a76b0SSuyog Pawar /*****************************************************************************/
43*c83a76b0SSuyog Pawar #define CBR_BIT_ALLOC_PERIOD 1
44*c83a76b0SSuyog Pawar #define MAX_SCENE_NUM_RC 30
45*c83a76b0SSuyog Pawar #define HALF_MAX_SCENE_NUM_RC MAX_SCENE_NUM_RC / 2
46*c83a76b0SSuyog Pawar 
47*c83a76b0SSuyog Pawar /*****************************************************************************/
48*c83a76b0SSuyog Pawar /* Structure                                                                 */
49*c83a76b0SSuyog Pawar /*****************************************************************************/
50*c83a76b0SSuyog Pawar /* Rate control state structure */
51*c83a76b0SSuyog Pawar typedef struct rate_control_api_t
52*c83a76b0SSuyog Pawar {
53*c83a76b0SSuyog Pawar     rc_type_e e_rc_type; /* RC Algorithm */
54*c83a76b0SSuyog Pawar     UWORD8 u1_is_mb_level_rc_on; /* Whether MB level rc is enabled or not */
55*c83a76b0SSuyog Pawar     /* rate_control_param_t s_rate_control_param;                 Store a copy of input parameters for re-initialisation */
56*c83a76b0SSuyog Pawar     pic_handling_handle ps_pic_handling; /* Picture handling struct */
57*c83a76b0SSuyog Pawar     rc_rd_model_handle aps_rd_model[MAX_PIC_TYPE]; /* Model struct for I and P frms */
58*c83a76b0SSuyog Pawar     vbr_storage_vbv_handle ps_vbr_storage_vbv; /* VBR storage VBV structure */
59*c83a76b0SSuyog Pawar     est_sad_handle ps_est_sad; /* Calculate the estimated SAD */
60*c83a76b0SSuyog Pawar     bit_allocation_handle ps_bit_allocation; /* Allocation of bits for each frame */
61*c83a76b0SSuyog Pawar     mb_rate_control_handle ps_mb_rate_control; /* MB Level rate control state structure */
62*c83a76b0SSuyog Pawar     sad_acc_handle ps_sad_acc; /* Sad accumulator */
63*c83a76b0SSuyog Pawar     UWORD8 au1_is_first_frm_coded[MAX_PIC_TYPE];
64*c83a76b0SSuyog Pawar     WORD32 ai4_prev_frm_qp[MAX_SCENE_NUM_RC][MAX_PIC_TYPE];
65*c83a76b0SSuyog Pawar     WORD32 ai4_prev_frm_qp_q6[MAX_SCENE_NUM_RC][MAX_PIC_TYPE];
66*c83a76b0SSuyog Pawar 
67*c83a76b0SSuyog Pawar     cbr_buffer_handle ps_cbr_buffer;
68*c83a76b0SSuyog Pawar     UWORD8 au1_avg_bitrate_changed[MAX_PIC_TYPE];
69*c83a76b0SSuyog Pawar     UWORD8 u1_is_first_frm;
70*c83a76b0SSuyog Pawar     /* UWORD8               au1_min_max_qp[(MAX_PIC_TYPE << 1)]; */
71*c83a76b0SSuyog Pawar     WORD32 ai4_min_qp[MAX_PIC_TYPE];
72*c83a76b0SSuyog Pawar     WORD32 ai4_max_qp[MAX_PIC_TYPE];
73*c83a76b0SSuyog Pawar     WORD32 ai4_max_qp_q6[MAX_PIC_TYPE];
74*c83a76b0SSuyog Pawar     WORD32 ai4_min_qp_q6[MAX_PIC_TYPE];
75*c83a76b0SSuyog Pawar 
76*c83a76b0SSuyog Pawar     WORD32 i4_prev_frm_est_bits;
77*c83a76b0SSuyog Pawar     WORD32 i4_orig_frm_est_bits;
78*c83a76b0SSuyog Pawar     vbr_str_prms_t s_vbr_str_prms;
79*c83a76b0SSuyog Pawar     init_qp_handle ps_init_qp;
80*c83a76b0SSuyog Pawar     /* Store the values which are to be impacted after a delay */
81*c83a76b0SSuyog Pawar     UWORD32 u4_frms_in_delay_prd_for_peak_bit_rate_change;
82*c83a76b0SSuyog Pawar     UWORD32 au4_new_peak_bit_rate[MAX_NUM_DRAIN_RATES];
83*c83a76b0SSuyog Pawar     picture_type_e prev_ref_pic_type;
84*c83a76b0SSuyog Pawar     WORD32 i4_P_to_I_ratio;
85*c83a76b0SSuyog Pawar     WORD32 ai4_min_texture_bits[MAX_PIC_TYPE];
86*c83a76b0SSuyog Pawar     /* Complexity based buffer movement */
87*c83a76b0SSuyog Pawar     WORD32 i4_prev_ref_is_scd;
88*c83a76b0SSuyog Pawar     WORD32 i4_is_hbr; /*Flag to indicate CBR_NLDRC_HBR*/
89*c83a76b0SSuyog Pawar     WORD32 i4_num_active_pic_type;
90*c83a76b0SSuyog Pawar     WORD32 i4_lap_f_sim;
91*c83a76b0SSuyog Pawar     WORD32 i4_quality_preset;
92*c83a76b0SSuyog Pawar     WORD32 i4_scd_I_frame_estimated_tot_bits;
93*c83a76b0SSuyog Pawar     WORD32 i4_I_frame_qp_model; /*offline = 0, online = 1*/
94*c83a76b0SSuyog Pawar     LWORD64 i8_per_pixel_p_frm_hme_sad_q10;
95*c83a76b0SSuyog Pawar     UWORD32 u4_min_scd_hevc_qp;
96*c83a76b0SSuyog Pawar     UWORD32 u4_bit_depth_based_max_qp;
97*c83a76b0SSuyog Pawar     UWORD8 u1_bit_depth;
98*c83a76b0SSuyog Pawar     FILE *pf_rc_stat_file;
99*c83a76b0SSuyog Pawar     WORD32 i4_rc_pass; /*variable to differentiate first pass and second pass*/
100*c83a76b0SSuyog Pawar     WORD32 i4_max_frame_width;
101*c83a76b0SSuyog Pawar     WORD32 i4_max_frame_height;
102*c83a76b0SSuyog Pawar     void *pv_2pass_gop_summary;
103*c83a76b0SSuyog Pawar     WORD32 i4_num_gop;
104*c83a76b0SSuyog Pawar     void *pv_rc_sys_api;
105*c83a76b0SSuyog Pawar     /*In static cases signal the future underflow warning to lower the qp*/
106*c83a76b0SSuyog Pawar     WORD32 i4_underflow_warning;
107*c83a76b0SSuyog Pawar     float f_max_hme_sad_per_pixel;
108*c83a76b0SSuyog Pawar     /*f_p_to_i_comp_ratio is for comparison of pre intra complexity of  i & p frames
109*c83a76b0SSuyog Pawar     It is used for jacking up of p frame qp if i frame was
110*c83a76b0SSuyog Pawar     extremely simple to avoid overconsumption of bits in p frame*/
111*c83a76b0SSuyog Pawar     float f_p_to_i_comp_ratio;
112*c83a76b0SSuyog Pawar     /*i4_scd_in_period_2_pass is used to signal the scd in period for 2 pass
113*c83a76b0SSuyog Pawar     this signal is one of the criteria for clipping the sudden increase of qp*/
114*c83a76b0SSuyog Pawar     WORD32 i4_scd_in_period_2_pass;
115*c83a76b0SSuyog Pawar     WORD32 i4_is_infinite_gop;
116*c83a76b0SSuyog Pawar     WORD32 i4_frames_since_last_scd;
117*c83a76b0SSuyog Pawar     WORD32 i4_num_frame_parallel;
118*c83a76b0SSuyog Pawar     WORD32 ai4_est_tot_bits[MAX_NUM_FRAME_PARALLEL];
119*c83a76b0SSuyog Pawar     WORD32 i4_capped_vbr_flag;
120*c83a76b0SSuyog Pawar } rate_control_api_t;
121*c83a76b0SSuyog Pawar 
122*c83a76b0SSuyog Pawar #endif /*_RATE_CONTROL_API_STRUCTS_H_*/
123