xref: /aosp_15_r20/external/libffi/src/powerpc/aix_closure.S (revision 1fd5a2e1d639cd1ddf29dd0c484c123bbd850c21)
1*1fd5a2e1SPrashanth Swaminathan/* -----------------------------------------------------------------------
2*1fd5a2e1SPrashanth Swaminathan   aix_closure.S - Copyright (c) 2002, 2003, 2009 Free Software Foundation, Inc.
3*1fd5a2e1SPrashanth Swaminathan   based on darwin_closure.S
4*1fd5a2e1SPrashanth Swaminathan
5*1fd5a2e1SPrashanth Swaminathan   PowerPC Assembly glue.
6*1fd5a2e1SPrashanth Swaminathan
7*1fd5a2e1SPrashanth Swaminathan   Permission is hereby granted, free of charge, to any person obtaining
8*1fd5a2e1SPrashanth Swaminathan   a copy of this software and associated documentation files (the
9*1fd5a2e1SPrashanth Swaminathan   ``Software''), to deal in the Software without restriction, including
10*1fd5a2e1SPrashanth Swaminathan   without limitation the rights to use, copy, modify, merge, publish,
11*1fd5a2e1SPrashanth Swaminathan   distribute, sublicense, and/or sell copies of the Software, and to
12*1fd5a2e1SPrashanth Swaminathan   permit persons to whom the Software is furnished to do so, subject to
13*1fd5a2e1SPrashanth Swaminathan   the following conditions:
14*1fd5a2e1SPrashanth Swaminathan
15*1fd5a2e1SPrashanth Swaminathan   The above copyright notice and this permission notice shall be included
16*1fd5a2e1SPrashanth Swaminathan   in all copies or substantial portions of the Software.
17*1fd5a2e1SPrashanth Swaminathan
18*1fd5a2e1SPrashanth Swaminathan   THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
19*1fd5a2e1SPrashanth Swaminathan   OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20*1fd5a2e1SPrashanth Swaminathan   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21*1fd5a2e1SPrashanth Swaminathan   IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR
22*1fd5a2e1SPrashanth Swaminathan   OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23*1fd5a2e1SPrashanth Swaminathan   ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24*1fd5a2e1SPrashanth Swaminathan   OTHER DEALINGS IN THE SOFTWARE.
25*1fd5a2e1SPrashanth Swaminathan   ----------------------------------------------------------------------- */
26*1fd5a2e1SPrashanth Swaminathan
27*1fd5a2e1SPrashanth Swaminathan	.set r0,0
28*1fd5a2e1SPrashanth Swaminathan	.set r1,1
29*1fd5a2e1SPrashanth Swaminathan	.set r2,2
30*1fd5a2e1SPrashanth Swaminathan	.set r3,3
31*1fd5a2e1SPrashanth Swaminathan	.set r4,4
32*1fd5a2e1SPrashanth Swaminathan	.set r5,5
33*1fd5a2e1SPrashanth Swaminathan	.set r6,6
34*1fd5a2e1SPrashanth Swaminathan	.set r7,7
35*1fd5a2e1SPrashanth Swaminathan	.set r8,8
36*1fd5a2e1SPrashanth Swaminathan	.set r9,9
37*1fd5a2e1SPrashanth Swaminathan	.set r10,10
38*1fd5a2e1SPrashanth Swaminathan	.set r11,11
39*1fd5a2e1SPrashanth Swaminathan	.set r12,12
40*1fd5a2e1SPrashanth Swaminathan	.set r13,13
41*1fd5a2e1SPrashanth Swaminathan	.set r14,14
42*1fd5a2e1SPrashanth Swaminathan	.set r15,15
43*1fd5a2e1SPrashanth Swaminathan	.set r16,16
44*1fd5a2e1SPrashanth Swaminathan	.set r17,17
45*1fd5a2e1SPrashanth Swaminathan	.set r18,18
46*1fd5a2e1SPrashanth Swaminathan	.set r19,19
47*1fd5a2e1SPrashanth Swaminathan	.set r20,20
48*1fd5a2e1SPrashanth Swaminathan	.set r21,21
49*1fd5a2e1SPrashanth Swaminathan	.set r22,22
50*1fd5a2e1SPrashanth Swaminathan	.set r23,23
51*1fd5a2e1SPrashanth Swaminathan	.set r24,24
52*1fd5a2e1SPrashanth Swaminathan	.set r25,25
53*1fd5a2e1SPrashanth Swaminathan	.set r26,26
54*1fd5a2e1SPrashanth Swaminathan	.set r27,27
55*1fd5a2e1SPrashanth Swaminathan	.set r28,28
56*1fd5a2e1SPrashanth Swaminathan	.set r29,29
57*1fd5a2e1SPrashanth Swaminathan	.set r30,30
58*1fd5a2e1SPrashanth Swaminathan	.set r31,31
59*1fd5a2e1SPrashanth Swaminathan	.set f0,0
60*1fd5a2e1SPrashanth Swaminathan	.set f1,1
61*1fd5a2e1SPrashanth Swaminathan	.set f2,2
62*1fd5a2e1SPrashanth Swaminathan	.set f3,3
63*1fd5a2e1SPrashanth Swaminathan	.set f4,4
64*1fd5a2e1SPrashanth Swaminathan	.set f5,5
65*1fd5a2e1SPrashanth Swaminathan	.set f6,6
66*1fd5a2e1SPrashanth Swaminathan	.set f7,7
67*1fd5a2e1SPrashanth Swaminathan	.set f8,8
68*1fd5a2e1SPrashanth Swaminathan	.set f9,9
69*1fd5a2e1SPrashanth Swaminathan	.set f10,10
70*1fd5a2e1SPrashanth Swaminathan	.set f11,11
71*1fd5a2e1SPrashanth Swaminathan	.set f12,12
72*1fd5a2e1SPrashanth Swaminathan	.set f13,13
73*1fd5a2e1SPrashanth Swaminathan	.set f14,14
74*1fd5a2e1SPrashanth Swaminathan	.set f15,15
75*1fd5a2e1SPrashanth Swaminathan	.set f16,16
76*1fd5a2e1SPrashanth Swaminathan	.set f17,17
77*1fd5a2e1SPrashanth Swaminathan	.set f18,18
78*1fd5a2e1SPrashanth Swaminathan	.set f19,19
79*1fd5a2e1SPrashanth Swaminathan	.set f20,20
80*1fd5a2e1SPrashanth Swaminathan	.set f21,21
81*1fd5a2e1SPrashanth Swaminathan
82*1fd5a2e1SPrashanth Swaminathan	.extern .ffi_closure_helper_DARWIN
83*1fd5a2e1SPrashanth Swaminathan	.extern .ffi_go_closure_helper_DARWIN
84*1fd5a2e1SPrashanth Swaminathan
85*1fd5a2e1SPrashanth Swaminathan#define LIBFFI_ASM
86*1fd5a2e1SPrashanth Swaminathan#define JUMPTARGET(name) name
87*1fd5a2e1SPrashanth Swaminathan#define L(x) x
88*1fd5a2e1SPrashanth Swaminathan	.file "aix_closure.S"
89*1fd5a2e1SPrashanth Swaminathan	.toc
90*1fd5a2e1SPrashanth SwaminathanLC..60:
91*1fd5a2e1SPrashanth Swaminathan	.tc L..60[TC],L..60
92*1fd5a2e1SPrashanth Swaminathan	.csect .text[PR]
93*1fd5a2e1SPrashanth Swaminathan	.align 2
94*1fd5a2e1SPrashanth Swaminathan
95*1fd5a2e1SPrashanth Swaminathan.csect .text[PR]
96*1fd5a2e1SPrashanth Swaminathan	.align 2
97*1fd5a2e1SPrashanth Swaminathan	.globl ffi_closure_ASM
98*1fd5a2e1SPrashanth Swaminathan	.globl .ffi_closure_ASM
99*1fd5a2e1SPrashanth Swaminathan.csect ffi_closure_ASM[DS]
100*1fd5a2e1SPrashanth Swaminathanffi_closure_ASM:
101*1fd5a2e1SPrashanth Swaminathan#ifdef __64BIT__
102*1fd5a2e1SPrashanth Swaminathan	.llong .ffi_closure_ASM, TOC[tc0], 0
103*1fd5a2e1SPrashanth Swaminathan	.csect .text[PR]
104*1fd5a2e1SPrashanth Swaminathan.ffi_closure_ASM:
105*1fd5a2e1SPrashanth Swaminathan	.function .ffi_closure_ASM,.ffi_closure_ASM,16,044,LFE..0-LFB..0
106*1fd5a2e1SPrashanth Swaminathan	.bf __LINE__
107*1fd5a2e1SPrashanth Swaminathan	.line 1
108*1fd5a2e1SPrashanth SwaminathanLFB..0:
109*1fd5a2e1SPrashanth Swaminathan/* we want to build up an area for the parameters passed */
110*1fd5a2e1SPrashanth Swaminathan/* in registers (both floating point and integer) */
111*1fd5a2e1SPrashanth Swaminathan
112*1fd5a2e1SPrashanth Swaminathan	/* we store gpr 3 to gpr 10 (aligned to 4)
113*1fd5a2e1SPrashanth Swaminathan	in the parents outgoing area  */
114*1fd5a2e1SPrashanth Swaminathan	std   r3, 48+(0*8)(r1)
115*1fd5a2e1SPrashanth Swaminathan	std   r4, 48+(1*8)(r1)
116*1fd5a2e1SPrashanth Swaminathan	std   r5, 48+(2*8)(r1)
117*1fd5a2e1SPrashanth Swaminathan	std   r6, 48+(3*8)(r1)
118*1fd5a2e1SPrashanth Swaminathan	mflr  r0
119*1fd5a2e1SPrashanth Swaminathan
120*1fd5a2e1SPrashanth Swaminathan	std   r7, 48+(4*8)(r1)
121*1fd5a2e1SPrashanth Swaminathan	std   r8, 48+(5*8)(r1)
122*1fd5a2e1SPrashanth Swaminathan	std   r9, 48+(6*8)(r1)
123*1fd5a2e1SPrashanth Swaminathan	std   r10, 48+(7*8)(r1)
124*1fd5a2e1SPrashanth Swaminathan	std   r0, 16(r1)	/* save the return address */
125*1fd5a2e1SPrashanth SwaminathanLCFI..0:
126*1fd5a2e1SPrashanth Swaminathan	/* 48  Bytes (Linkage Area) */
127*1fd5a2e1SPrashanth Swaminathan	/* 64  Bytes (params) */
128*1fd5a2e1SPrashanth Swaminathan	/* 16  Bytes (result) */
129*1fd5a2e1SPrashanth Swaminathan	/* 104 Bytes (13*8 from FPR) */
130*1fd5a2e1SPrashanth Swaminathan	/* 8   Bytes (alignment) */
131*1fd5a2e1SPrashanth Swaminathan	/* 240 Bytes */
132*1fd5a2e1SPrashanth Swaminathan
133*1fd5a2e1SPrashanth Swaminathan	stdu  r1, -240(r1)	/* skip over caller save area
134*1fd5a2e1SPrashanth Swaminathan				   keep stack aligned to 16  */
135*1fd5a2e1SPrashanth SwaminathanLCFI..1:
136*1fd5a2e1SPrashanth Swaminathan
137*1fd5a2e1SPrashanth Swaminathan	/* next save fpr 1 to fpr 13 (aligned to 8) */
138*1fd5a2e1SPrashanth Swaminathan	stfd  f1, 128+(0*8)(r1)
139*1fd5a2e1SPrashanth Swaminathan	stfd  f2, 128+(1*8)(r1)
140*1fd5a2e1SPrashanth Swaminathan	stfd  f3, 128+(2*8)(r1)
141*1fd5a2e1SPrashanth Swaminathan	stfd  f4, 128+(3*8)(r1)
142*1fd5a2e1SPrashanth Swaminathan	stfd  f5, 128+(4*8)(r1)
143*1fd5a2e1SPrashanth Swaminathan	stfd  f6, 128+(5*8)(r1)
144*1fd5a2e1SPrashanth Swaminathan	stfd  f7, 128+(6*8)(r1)
145*1fd5a2e1SPrashanth Swaminathan	stfd  f8, 128+(7*8)(r1)
146*1fd5a2e1SPrashanth Swaminathan	stfd  f9, 128+(8*8)(r1)
147*1fd5a2e1SPrashanth Swaminathan	stfd  f10, 128+(9*8)(r1)
148*1fd5a2e1SPrashanth Swaminathan	stfd  f11, 128+(10*8)(r1)
149*1fd5a2e1SPrashanth Swaminathan	stfd  f12, 128+(11*8)(r1)
150*1fd5a2e1SPrashanth Swaminathan	stfd  f13, 128+(12*8)(r1)
151*1fd5a2e1SPrashanth Swaminathan
152*1fd5a2e1SPrashanth Swaminathan	/* set up registers for the routine that actually does the work */
153*1fd5a2e1SPrashanth Swaminathan	/* get the context pointer from the trampoline */
154*1fd5a2e1SPrashanth Swaminathan	mr r3, r11
155*1fd5a2e1SPrashanth Swaminathan
156*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the result storage */
157*1fd5a2e1SPrashanth Swaminathan	addi r4, r1, 112
158*1fd5a2e1SPrashanth Swaminathan
159*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the saved gpr registers */
160*1fd5a2e1SPrashanth Swaminathan	addi r5, r1, 288
161*1fd5a2e1SPrashanth Swaminathan
162*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the saved fpr registers */
163*1fd5a2e1SPrashanth Swaminathan	addi r6, r1, 128
164*1fd5a2e1SPrashanth Swaminathan
165*1fd5a2e1SPrashanth Swaminathan	/* make the call */
166*1fd5a2e1SPrashanth Swaminathan	bl .ffi_closure_helper_DARWIN
167*1fd5a2e1SPrashanth Swaminathan	nop
168*1fd5a2e1SPrashanth Swaminathan
169*1fd5a2e1SPrashanth Swaminathan.Ldoneclosure:
170*1fd5a2e1SPrashanth Swaminathan
171*1fd5a2e1SPrashanth Swaminathan	/* now r3 contains the return type */
172*1fd5a2e1SPrashanth Swaminathan	/* so use it to look up in a table */
173*1fd5a2e1SPrashanth Swaminathan	/* so we know how to deal with each type */
174*1fd5a2e1SPrashanth Swaminathan
175*1fd5a2e1SPrashanth Swaminathan	/* look up the proper starting point in table  */
176*1fd5a2e1SPrashanth Swaminathan	/* by using return type as offset */
177*1fd5a2e1SPrashanth Swaminathan	lhz	r3, 10(r3)	/* load type from return type */
178*1fd5a2e1SPrashanth Swaminathan	ld	r4, LC..60(2)	/* get address of jump table */
179*1fd5a2e1SPrashanth Swaminathan	sldi	r3, r3, 4	/* now multiply return type by 16 */
180*1fd5a2e1SPrashanth Swaminathan	ld	r0, 240+16(r1)	/* load return address */
181*1fd5a2e1SPrashanth Swaminathan	add	r3, r3, r4	/* add contents of table to table address */
182*1fd5a2e1SPrashanth Swaminathan	mtctr	r3
183*1fd5a2e1SPrashanth Swaminathan	bctr			/* jump to it */
184*1fd5a2e1SPrashanth Swaminathan
185*1fd5a2e1SPrashanth Swaminathan/* Each fragment must be exactly 16 bytes long (4 instructions).
186*1fd5a2e1SPrashanth Swaminathan   Align to 16 byte boundary for cache and dispatch efficiency.  */
187*1fd5a2e1SPrashanth Swaminathan	.align 4
188*1fd5a2e1SPrashanth Swaminathan
189*1fd5a2e1SPrashanth SwaminathanL..60:
190*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_VOID */
191*1fd5a2e1SPrashanth Swaminathan	mtlr r0
192*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
193*1fd5a2e1SPrashanth Swaminathan	blr
194*1fd5a2e1SPrashanth Swaminathan	nop
195*1fd5a2e1SPrashanth Swaminathan
196*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_INT */
197*1fd5a2e1SPrashanth Swaminathan	lwa r3, 112+4(r1)
198*1fd5a2e1SPrashanth Swaminathan	mtlr r0
199*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
200*1fd5a2e1SPrashanth Swaminathan	blr
201*1fd5a2e1SPrashanth Swaminathan
202*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_FLOAT */
203*1fd5a2e1SPrashanth Swaminathan	lfs f1, 112+0(r1)
204*1fd5a2e1SPrashanth Swaminathan	mtlr r0
205*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
206*1fd5a2e1SPrashanth Swaminathan	blr
207*1fd5a2e1SPrashanth Swaminathan
208*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_DOUBLE */
209*1fd5a2e1SPrashanth Swaminathan	lfd f1, 112+0(r1)
210*1fd5a2e1SPrashanth Swaminathan	mtlr r0
211*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
212*1fd5a2e1SPrashanth Swaminathan	blr
213*1fd5a2e1SPrashanth Swaminathan
214*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_LONGDOUBLE */
215*1fd5a2e1SPrashanth Swaminathan	lfd f1, 112+0(r1)
216*1fd5a2e1SPrashanth Swaminathan	mtlr r0
217*1fd5a2e1SPrashanth Swaminathan	lfd f2, 112+8(r1)
218*1fd5a2e1SPrashanth Swaminathan	b L..finish
219*1fd5a2e1SPrashanth Swaminathan
220*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_UINT8 */
221*1fd5a2e1SPrashanth Swaminathan	lbz r3, 112+7(r1)
222*1fd5a2e1SPrashanth Swaminathan	mtlr r0
223*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
224*1fd5a2e1SPrashanth Swaminathan	blr
225*1fd5a2e1SPrashanth Swaminathan
226*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_SINT8 */
227*1fd5a2e1SPrashanth Swaminathan	lbz r3, 112+7(r1)
228*1fd5a2e1SPrashanth Swaminathan	mtlr r0
229*1fd5a2e1SPrashanth Swaminathan	extsb r3, r3
230*1fd5a2e1SPrashanth Swaminathan	b L..finish
231*1fd5a2e1SPrashanth Swaminathan
232*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_UINT16 */
233*1fd5a2e1SPrashanth Swaminathan	lhz r3, 112+6(r1)
234*1fd5a2e1SPrashanth Swaminathan	mtlr r0
235*1fd5a2e1SPrashanth SwaminathanL..finish:
236*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
237*1fd5a2e1SPrashanth Swaminathan	blr
238*1fd5a2e1SPrashanth Swaminathan
239*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_SINT16 */
240*1fd5a2e1SPrashanth Swaminathan	lha r3, 112+6(r1)
241*1fd5a2e1SPrashanth Swaminathan	mtlr r0
242*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
243*1fd5a2e1SPrashanth Swaminathan	blr
244*1fd5a2e1SPrashanth Swaminathan
245*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_UINT32 */
246*1fd5a2e1SPrashanth Swaminathan	lwz r3, 112+4(r1)
247*1fd5a2e1SPrashanth Swaminathan	mtlr r0
248*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
249*1fd5a2e1SPrashanth Swaminathan	blr
250*1fd5a2e1SPrashanth Swaminathan
251*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_SINT32 */
252*1fd5a2e1SPrashanth Swaminathan	lwa r3, 112+4(r1)
253*1fd5a2e1SPrashanth Swaminathan	mtlr r0
254*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
255*1fd5a2e1SPrashanth Swaminathan	blr
256*1fd5a2e1SPrashanth Swaminathan
257*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_UINT64 */
258*1fd5a2e1SPrashanth Swaminathan	ld r3, 112+0(r1)
259*1fd5a2e1SPrashanth Swaminathan	mtlr r0
260*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
261*1fd5a2e1SPrashanth Swaminathan	blr
262*1fd5a2e1SPrashanth Swaminathan
263*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_SINT64 */
264*1fd5a2e1SPrashanth Swaminathan	ld r3, 112+0(r1)
265*1fd5a2e1SPrashanth Swaminathan	mtlr r0
266*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
267*1fd5a2e1SPrashanth Swaminathan	blr
268*1fd5a2e1SPrashanth Swaminathan
269*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_STRUCT */
270*1fd5a2e1SPrashanth Swaminathan	mtlr r0
271*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
272*1fd5a2e1SPrashanth Swaminathan	blr
273*1fd5a2e1SPrashanth Swaminathan	nop
274*1fd5a2e1SPrashanth Swaminathan
275*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_POINTER */
276*1fd5a2e1SPrashanth Swaminathan	ld r3, 112+0(r1)
277*1fd5a2e1SPrashanth Swaminathan	mtlr r0
278*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 240
279*1fd5a2e1SPrashanth Swaminathan	blr
280*1fd5a2e1SPrashanth SwaminathanLFE..0:
281*1fd5a2e1SPrashanth Swaminathan
282*1fd5a2e1SPrashanth Swaminathan#else /* ! __64BIT__ */
283*1fd5a2e1SPrashanth Swaminathan
284*1fd5a2e1SPrashanth Swaminathan	.long .ffi_closure_ASM, TOC[tc0], 0
285*1fd5a2e1SPrashanth Swaminathan	.csect .text[PR]
286*1fd5a2e1SPrashanth Swaminathan.ffi_closure_ASM:
287*1fd5a2e1SPrashanth Swaminathan	.function .ffi_closure_ASM,.ffi_closure_ASM,16,044,LFE..0-LFB..0
288*1fd5a2e1SPrashanth Swaminathan	.bf __LINE__
289*1fd5a2e1SPrashanth Swaminathan	.line 1
290*1fd5a2e1SPrashanth SwaminathanLFB..0:
291*1fd5a2e1SPrashanth Swaminathan/* we want to build up an area for the parameters passed */
292*1fd5a2e1SPrashanth Swaminathan/* in registers (both floating point and integer) */
293*1fd5a2e1SPrashanth Swaminathan
294*1fd5a2e1SPrashanth Swaminathan	/* we store gpr 3 to gpr 10 (aligned to 4)
295*1fd5a2e1SPrashanth Swaminathan	in the parents outgoing area  */
296*1fd5a2e1SPrashanth Swaminathan	stw   r3, 24+(0*4)(r1)
297*1fd5a2e1SPrashanth Swaminathan	stw   r4, 24+(1*4)(r1)
298*1fd5a2e1SPrashanth Swaminathan	stw   r5, 24+(2*4)(r1)
299*1fd5a2e1SPrashanth Swaminathan	stw   r6, 24+(3*4)(r1)
300*1fd5a2e1SPrashanth Swaminathan	mflr  r0
301*1fd5a2e1SPrashanth Swaminathan
302*1fd5a2e1SPrashanth Swaminathan	stw   r7, 24+(4*4)(r1)
303*1fd5a2e1SPrashanth Swaminathan	stw   r8, 24+(5*4)(r1)
304*1fd5a2e1SPrashanth Swaminathan	stw   r9, 24+(6*4)(r1)
305*1fd5a2e1SPrashanth Swaminathan	stw   r10, 24+(7*4)(r1)
306*1fd5a2e1SPrashanth Swaminathan	stw   r0, 8(r1)
307*1fd5a2e1SPrashanth SwaminathanLCFI..0:
308*1fd5a2e1SPrashanth Swaminathan	/* 24 Bytes (Linkage Area) */
309*1fd5a2e1SPrashanth Swaminathan	/* 32 Bytes (params) */
310*1fd5a2e1SPrashanth Swaminathan	/* 16  Bytes (result) */
311*1fd5a2e1SPrashanth Swaminathan	/* 104 Bytes (13*8 from FPR) */
312*1fd5a2e1SPrashanth Swaminathan	/* 176 Bytes */
313*1fd5a2e1SPrashanth Swaminathan
314*1fd5a2e1SPrashanth Swaminathan	stwu  r1, -176(r1)	/* skip over caller save area
315*1fd5a2e1SPrashanth Swaminathan				   keep stack aligned to 16  */
316*1fd5a2e1SPrashanth SwaminathanLCFI..1:
317*1fd5a2e1SPrashanth Swaminathan
318*1fd5a2e1SPrashanth Swaminathan	/* next save fpr 1 to fpr 13 (aligned to 8) */
319*1fd5a2e1SPrashanth Swaminathan	stfd  f1, 72+(0*8)(r1)
320*1fd5a2e1SPrashanth Swaminathan	stfd  f2, 72+(1*8)(r1)
321*1fd5a2e1SPrashanth Swaminathan	stfd  f3, 72+(2*8)(r1)
322*1fd5a2e1SPrashanth Swaminathan	stfd  f4, 72+(3*8)(r1)
323*1fd5a2e1SPrashanth Swaminathan	stfd  f5, 72+(4*8)(r1)
324*1fd5a2e1SPrashanth Swaminathan	stfd  f6, 72+(5*8)(r1)
325*1fd5a2e1SPrashanth Swaminathan	stfd  f7, 72+(6*8)(r1)
326*1fd5a2e1SPrashanth Swaminathan	stfd  f8, 72+(7*8)(r1)
327*1fd5a2e1SPrashanth Swaminathan	stfd  f9, 72+(8*8)(r1)
328*1fd5a2e1SPrashanth Swaminathan	stfd  f10, 72+(9*8)(r1)
329*1fd5a2e1SPrashanth Swaminathan	stfd  f11, 72+(10*8)(r1)
330*1fd5a2e1SPrashanth Swaminathan	stfd  f12, 72+(11*8)(r1)
331*1fd5a2e1SPrashanth Swaminathan	stfd  f13, 72+(12*8)(r1)
332*1fd5a2e1SPrashanth Swaminathan
333*1fd5a2e1SPrashanth Swaminathan	/* set up registers for the routine that actually does the work */
334*1fd5a2e1SPrashanth Swaminathan	/* get the context pointer from the trampoline */
335*1fd5a2e1SPrashanth Swaminathan	mr r3, r11
336*1fd5a2e1SPrashanth Swaminathan
337*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the result storage */
338*1fd5a2e1SPrashanth Swaminathan	addi r4, r1, 56
339*1fd5a2e1SPrashanth Swaminathan
340*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the saved gpr registers */
341*1fd5a2e1SPrashanth Swaminathan	addi r5, r1, 200
342*1fd5a2e1SPrashanth Swaminathan
343*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the saved fpr registers */
344*1fd5a2e1SPrashanth Swaminathan	addi r6, r1, 72
345*1fd5a2e1SPrashanth Swaminathan
346*1fd5a2e1SPrashanth Swaminathan	/* make the call */
347*1fd5a2e1SPrashanth Swaminathan	bl .ffi_closure_helper_DARWIN
348*1fd5a2e1SPrashanth Swaminathan	nop
349*1fd5a2e1SPrashanth Swaminathan
350*1fd5a2e1SPrashanth Swaminathan.Ldoneclosure:
351*1fd5a2e1SPrashanth Swaminathan
352*1fd5a2e1SPrashanth Swaminathan	/* now r3 contains the return type */
353*1fd5a2e1SPrashanth Swaminathan	/* so use it to look up in a table */
354*1fd5a2e1SPrashanth Swaminathan	/* so we know how to deal with each type */
355*1fd5a2e1SPrashanth Swaminathan
356*1fd5a2e1SPrashanth Swaminathan	/* look up the proper starting point in table  */
357*1fd5a2e1SPrashanth Swaminathan	/* by using return type as offset */
358*1fd5a2e1SPrashanth Swaminathan	lhz	r3, 6(r3)	/* load type from return type */
359*1fd5a2e1SPrashanth Swaminathan	lwz	r4, LC..60(2)	/* get address of jump table */
360*1fd5a2e1SPrashanth Swaminathan	slwi	r3, r3, 4	/* now multiply return type by 16 */
361*1fd5a2e1SPrashanth Swaminathan	lwz	r0, 176+8(r1)	/* load return address */
362*1fd5a2e1SPrashanth Swaminathan	add	r3, r3, r4	/* add contents of table to table address */
363*1fd5a2e1SPrashanth Swaminathan	mtctr	r3
364*1fd5a2e1SPrashanth Swaminathan	bctr			/* jump to it */
365*1fd5a2e1SPrashanth Swaminathan
366*1fd5a2e1SPrashanth Swaminathan/* Each fragment must be exactly 16 bytes long (4 instructions).
367*1fd5a2e1SPrashanth Swaminathan   Align to 16 byte boundary for cache and dispatch efficiency.  */
368*1fd5a2e1SPrashanth Swaminathan	.align 4
369*1fd5a2e1SPrashanth Swaminathan
370*1fd5a2e1SPrashanth SwaminathanL..60:
371*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_VOID */
372*1fd5a2e1SPrashanth Swaminathan	mtlr r0
373*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 176
374*1fd5a2e1SPrashanth Swaminathan	blr
375*1fd5a2e1SPrashanth Swaminathan	nop
376*1fd5a2e1SPrashanth Swaminathan
377*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_INT */
378*1fd5a2e1SPrashanth Swaminathan	lwz r3, 56+0(r1)
379*1fd5a2e1SPrashanth Swaminathan	mtlr r0
380*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 176
381*1fd5a2e1SPrashanth Swaminathan	blr
382*1fd5a2e1SPrashanth Swaminathan
383*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_FLOAT */
384*1fd5a2e1SPrashanth Swaminathan	lfs f1, 56+0(r1)
385*1fd5a2e1SPrashanth Swaminathan	mtlr r0
386*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 176
387*1fd5a2e1SPrashanth Swaminathan	blr
388*1fd5a2e1SPrashanth Swaminathan
389*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_DOUBLE */
390*1fd5a2e1SPrashanth Swaminathan	lfd f1, 56+0(r1)
391*1fd5a2e1SPrashanth Swaminathan	mtlr r0
392*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 176
393*1fd5a2e1SPrashanth Swaminathan	blr
394*1fd5a2e1SPrashanth Swaminathan
395*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_LONGDOUBLE */
396*1fd5a2e1SPrashanth Swaminathan	lfd f1, 56+0(r1)
397*1fd5a2e1SPrashanth Swaminathan	mtlr r0
398*1fd5a2e1SPrashanth Swaminathan	lfd f2, 56+8(r1)
399*1fd5a2e1SPrashanth Swaminathan	b L..finish
400*1fd5a2e1SPrashanth Swaminathan
401*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_UINT8 */
402*1fd5a2e1SPrashanth Swaminathan	lbz r3, 56+3(r1)
403*1fd5a2e1SPrashanth Swaminathan	mtlr r0
404*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 176
405*1fd5a2e1SPrashanth Swaminathan	blr
406*1fd5a2e1SPrashanth Swaminathan
407*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_SINT8 */
408*1fd5a2e1SPrashanth Swaminathan	lbz r3, 56+3(r1)
409*1fd5a2e1SPrashanth Swaminathan	mtlr r0
410*1fd5a2e1SPrashanth Swaminathan	extsb r3, r3
411*1fd5a2e1SPrashanth Swaminathan	b L..finish
412*1fd5a2e1SPrashanth Swaminathan
413*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_UINT16 */
414*1fd5a2e1SPrashanth Swaminathan	lhz r3, 56+2(r1)
415*1fd5a2e1SPrashanth Swaminathan	mtlr r0
416*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 176
417*1fd5a2e1SPrashanth Swaminathan	blr
418*1fd5a2e1SPrashanth Swaminathan
419*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_SINT16 */
420*1fd5a2e1SPrashanth Swaminathan	lha r3, 56+2(r1)
421*1fd5a2e1SPrashanth Swaminathan	mtlr r0
422*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 176
423*1fd5a2e1SPrashanth Swaminathan	blr
424*1fd5a2e1SPrashanth Swaminathan
425*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_UINT32 */
426*1fd5a2e1SPrashanth Swaminathan	lwz r3, 56+0(r1)
427*1fd5a2e1SPrashanth Swaminathan	mtlr r0
428*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 176
429*1fd5a2e1SPrashanth Swaminathan	blr
430*1fd5a2e1SPrashanth Swaminathan
431*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_SINT32 */
432*1fd5a2e1SPrashanth Swaminathan	lwz r3, 56+0(r1)
433*1fd5a2e1SPrashanth Swaminathan	mtlr r0
434*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 176
435*1fd5a2e1SPrashanth Swaminathan	blr
436*1fd5a2e1SPrashanth Swaminathan
437*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_UINT64 */
438*1fd5a2e1SPrashanth Swaminathan	lwz r3, 56+0(r1)
439*1fd5a2e1SPrashanth Swaminathan	mtlr r0
440*1fd5a2e1SPrashanth Swaminathan	lwz r4, 56+4(r1)
441*1fd5a2e1SPrashanth Swaminathan	b L..finish
442*1fd5a2e1SPrashanth Swaminathan
443*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_SINT64 */
444*1fd5a2e1SPrashanth Swaminathan	lwz r3, 56+0(r1)
445*1fd5a2e1SPrashanth Swaminathan	mtlr r0
446*1fd5a2e1SPrashanth Swaminathan	lwz r4, 56+4(r1)
447*1fd5a2e1SPrashanth Swaminathan	b L..finish
448*1fd5a2e1SPrashanth Swaminathan
449*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_STRUCT */
450*1fd5a2e1SPrashanth Swaminathan	mtlr r0
451*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 176
452*1fd5a2e1SPrashanth Swaminathan	blr
453*1fd5a2e1SPrashanth Swaminathan	nop
454*1fd5a2e1SPrashanth Swaminathan
455*1fd5a2e1SPrashanth Swaminathan/* case FFI_TYPE_POINTER */
456*1fd5a2e1SPrashanth Swaminathan	lwz r3, 56+0(r1)
457*1fd5a2e1SPrashanth Swaminathan	mtlr r0
458*1fd5a2e1SPrashanth SwaminathanL..finish:
459*1fd5a2e1SPrashanth Swaminathan	addi r1, r1, 176
460*1fd5a2e1SPrashanth Swaminathan	blr
461*1fd5a2e1SPrashanth SwaminathanLFE..0:
462*1fd5a2e1SPrashanth Swaminathan#endif
463*1fd5a2e1SPrashanth Swaminathan	.ef __LINE__
464*1fd5a2e1SPrashanth Swaminathan/* END(ffi_closure_ASM) */
465*1fd5a2e1SPrashanth Swaminathan
466*1fd5a2e1SPrashanth Swaminathan
467*1fd5a2e1SPrashanth Swaminathan.csect .text[PR]
468*1fd5a2e1SPrashanth Swaminathan	.align 2
469*1fd5a2e1SPrashanth Swaminathan	.globl ffi_go_closure_ASM
470*1fd5a2e1SPrashanth Swaminathan	.globl .ffi_go_closure_ASM
471*1fd5a2e1SPrashanth Swaminathan.csect ffi_go_closure_ASM[DS]
472*1fd5a2e1SPrashanth Swaminathanffi_go_closure_ASM:
473*1fd5a2e1SPrashanth Swaminathan#ifdef __64BIT__
474*1fd5a2e1SPrashanth Swaminathan	.llong .ffi_go_closure_ASM, TOC[tc0], 0
475*1fd5a2e1SPrashanth Swaminathan	.csect .text[PR]
476*1fd5a2e1SPrashanth Swaminathan.ffi_go_closure_ASM:
477*1fd5a2e1SPrashanth Swaminathan	.function .ffi_go_closure_ASM,.ffi_go_closure_ASM,16,044,LFE..1-LFB..1
478*1fd5a2e1SPrashanth Swaminathan	.bf __LINE__
479*1fd5a2e1SPrashanth Swaminathan	.line 1
480*1fd5a2e1SPrashanth SwaminathanLFB..1:
481*1fd5a2e1SPrashanth Swaminathan/* we want to build up an area for the parameters passed */
482*1fd5a2e1SPrashanth Swaminathan/* in registers (both floating point and integer) */
483*1fd5a2e1SPrashanth Swaminathan
484*1fd5a2e1SPrashanth Swaminathan	/* we store gpr 3 to gpr 10 (aligned to 4)
485*1fd5a2e1SPrashanth Swaminathan	in the parents outgoing area  */
486*1fd5a2e1SPrashanth Swaminathan	std   r3, 48+(0*8)(r1)
487*1fd5a2e1SPrashanth Swaminathan	std   r4, 48+(1*8)(r1)
488*1fd5a2e1SPrashanth Swaminathan	std   r5, 48+(2*8)(r1)
489*1fd5a2e1SPrashanth Swaminathan	std   r6, 48+(3*8)(r1)
490*1fd5a2e1SPrashanth Swaminathan	mflr  r0
491*1fd5a2e1SPrashanth Swaminathan
492*1fd5a2e1SPrashanth Swaminathan	std   r7, 48+(4*8)(r1)
493*1fd5a2e1SPrashanth Swaminathan	std   r8, 48+(5*8)(r1)
494*1fd5a2e1SPrashanth Swaminathan	std   r9, 48+(6*8)(r1)
495*1fd5a2e1SPrashanth Swaminathan	std   r10, 48+(7*8)(r1)
496*1fd5a2e1SPrashanth Swaminathan	std   r0, 16(r1)	/* save the return address */
497*1fd5a2e1SPrashanth SwaminathanLCFI..2:
498*1fd5a2e1SPrashanth Swaminathan	/* 48  Bytes (Linkage Area) */
499*1fd5a2e1SPrashanth Swaminathan	/* 64  Bytes (params) */
500*1fd5a2e1SPrashanth Swaminathan	/* 16  Bytes (result) */
501*1fd5a2e1SPrashanth Swaminathan	/* 104 Bytes (13*8 from FPR) */
502*1fd5a2e1SPrashanth Swaminathan	/* 8   Bytes (alignment) */
503*1fd5a2e1SPrashanth Swaminathan	/* 240 Bytes */
504*1fd5a2e1SPrashanth Swaminathan
505*1fd5a2e1SPrashanth Swaminathan	stdu  r1, -240(r1)	/* skip over caller save area
506*1fd5a2e1SPrashanth Swaminathan				   keep stack aligned to 16  */
507*1fd5a2e1SPrashanth SwaminathanLCFI..3:
508*1fd5a2e1SPrashanth Swaminathan
509*1fd5a2e1SPrashanth Swaminathan	/* next save fpr 1 to fpr 13 (aligned to 8) */
510*1fd5a2e1SPrashanth Swaminathan	stfd  f1, 128+(0*8)(r1)
511*1fd5a2e1SPrashanth Swaminathan	stfd  f2, 128+(1*8)(r1)
512*1fd5a2e1SPrashanth Swaminathan	stfd  f3, 128+(2*8)(r1)
513*1fd5a2e1SPrashanth Swaminathan	stfd  f4, 128+(3*8)(r1)
514*1fd5a2e1SPrashanth Swaminathan	stfd  f5, 128+(4*8)(r1)
515*1fd5a2e1SPrashanth Swaminathan	stfd  f6, 128+(5*8)(r1)
516*1fd5a2e1SPrashanth Swaminathan	stfd  f7, 128+(6*8)(r1)
517*1fd5a2e1SPrashanth Swaminathan	stfd  f8, 128+(7*8)(r1)
518*1fd5a2e1SPrashanth Swaminathan	stfd  f9, 128+(8*8)(r1)
519*1fd5a2e1SPrashanth Swaminathan	stfd  f10, 128+(9*8)(r1)
520*1fd5a2e1SPrashanth Swaminathan	stfd  f11, 128+(10*8)(r1)
521*1fd5a2e1SPrashanth Swaminathan	stfd  f12, 128+(11*8)(r1)
522*1fd5a2e1SPrashanth Swaminathan	stfd  f13, 128+(12*8)(r1)
523*1fd5a2e1SPrashanth Swaminathan
524*1fd5a2e1SPrashanth Swaminathan	/* set up registers for the routine that actually does the work */
525*1fd5a2e1SPrashanth Swaminathan	mr r3, r11	/* go closure */
526*1fd5a2e1SPrashanth Swaminathan
527*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the result storage */
528*1fd5a2e1SPrashanth Swaminathan	addi r4, r1, 112
529*1fd5a2e1SPrashanth Swaminathan
530*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the saved gpr registers */
531*1fd5a2e1SPrashanth Swaminathan	addi r5, r1, 288
532*1fd5a2e1SPrashanth Swaminathan
533*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the saved fpr registers */
534*1fd5a2e1SPrashanth Swaminathan	addi r6, r1, 128
535*1fd5a2e1SPrashanth Swaminathan
536*1fd5a2e1SPrashanth Swaminathan	/* make the call */
537*1fd5a2e1SPrashanth Swaminathan	bl .ffi_go_closure_helper_DARWIN
538*1fd5a2e1SPrashanth Swaminathan	nop
539*1fd5a2e1SPrashanth Swaminathan
540*1fd5a2e1SPrashanth Swaminathan	b .Ldoneclosure
541*1fd5a2e1SPrashanth SwaminathanLFE..1:
542*1fd5a2e1SPrashanth Swaminathan
543*1fd5a2e1SPrashanth Swaminathan#else /* ! __64BIT__ */
544*1fd5a2e1SPrashanth Swaminathan
545*1fd5a2e1SPrashanth Swaminathan	.long .ffi_go_closure_ASM, TOC[tc0], 0
546*1fd5a2e1SPrashanth Swaminathan	.csect .text[PR]
547*1fd5a2e1SPrashanth Swaminathan.ffi_go_closure_ASM:
548*1fd5a2e1SPrashanth Swaminathan	.function .ffi_go_closure_ASM,.ffi_go_closure_ASM,16,044,LFE..1-LFB..1
549*1fd5a2e1SPrashanth Swaminathan	.bf __LINE__
550*1fd5a2e1SPrashanth Swaminathan	.line 1
551*1fd5a2e1SPrashanth SwaminathanLFB..1:
552*1fd5a2e1SPrashanth Swaminathan/* we want to build up an area for the parameters passed */
553*1fd5a2e1SPrashanth Swaminathan/* in registers (both floating point and integer) */
554*1fd5a2e1SPrashanth Swaminathan
555*1fd5a2e1SPrashanth Swaminathan	/* we store gpr 3 to gpr 10 (aligned to 4)
556*1fd5a2e1SPrashanth Swaminathan	in the parents outgoing area  */
557*1fd5a2e1SPrashanth Swaminathan	stw   r3, 24+(0*4)(r1)
558*1fd5a2e1SPrashanth Swaminathan	stw   r4, 24+(1*4)(r1)
559*1fd5a2e1SPrashanth Swaminathan	stw   r5, 24+(2*4)(r1)
560*1fd5a2e1SPrashanth Swaminathan	stw   r6, 24+(3*4)(r1)
561*1fd5a2e1SPrashanth Swaminathan	mflr  r0
562*1fd5a2e1SPrashanth Swaminathan
563*1fd5a2e1SPrashanth Swaminathan	stw   r7, 24+(4*4)(r1)
564*1fd5a2e1SPrashanth Swaminathan	stw   r8, 24+(5*4)(r1)
565*1fd5a2e1SPrashanth Swaminathan	stw   r9, 24+(6*4)(r1)
566*1fd5a2e1SPrashanth Swaminathan	stw   r10, 24+(7*4)(r1)
567*1fd5a2e1SPrashanth Swaminathan	stw   r0, 8(r1)
568*1fd5a2e1SPrashanth SwaminathanLCFI..2:
569*1fd5a2e1SPrashanth Swaminathan	/* 24 Bytes (Linkage Area) */
570*1fd5a2e1SPrashanth Swaminathan	/* 32 Bytes (params) */
571*1fd5a2e1SPrashanth Swaminathan	/* 16  Bytes (result) */
572*1fd5a2e1SPrashanth Swaminathan	/* 104 Bytes (13*8 from FPR) */
573*1fd5a2e1SPrashanth Swaminathan	/* 176 Bytes */
574*1fd5a2e1SPrashanth Swaminathan
575*1fd5a2e1SPrashanth Swaminathan	stwu  r1, -176(r1)	/* skip over caller save area
576*1fd5a2e1SPrashanth Swaminathan				   keep stack aligned to 16  */
577*1fd5a2e1SPrashanth SwaminathanLCFI..3:
578*1fd5a2e1SPrashanth Swaminathan
579*1fd5a2e1SPrashanth Swaminathan	/* next save fpr 1 to fpr 13 (aligned to 8) */
580*1fd5a2e1SPrashanth Swaminathan	stfd  f1, 72+(0*8)(r1)
581*1fd5a2e1SPrashanth Swaminathan	stfd  f2, 72+(1*8)(r1)
582*1fd5a2e1SPrashanth Swaminathan	stfd  f3, 72+(2*8)(r1)
583*1fd5a2e1SPrashanth Swaminathan	stfd  f4, 72+(3*8)(r1)
584*1fd5a2e1SPrashanth Swaminathan	stfd  f5, 72+(4*8)(r1)
585*1fd5a2e1SPrashanth Swaminathan	stfd  f6, 72+(5*8)(r1)
586*1fd5a2e1SPrashanth Swaminathan	stfd  f7, 72+(6*8)(r1)
587*1fd5a2e1SPrashanth Swaminathan	stfd  f8, 72+(7*8)(r1)
588*1fd5a2e1SPrashanth Swaminathan	stfd  f9, 72+(8*8)(r1)
589*1fd5a2e1SPrashanth Swaminathan	stfd  f10, 72+(9*8)(r1)
590*1fd5a2e1SPrashanth Swaminathan	stfd  f11, 72+(10*8)(r1)
591*1fd5a2e1SPrashanth Swaminathan	stfd  f12, 72+(11*8)(r1)
592*1fd5a2e1SPrashanth Swaminathan	stfd  f13, 72+(12*8)(r1)
593*1fd5a2e1SPrashanth Swaminathan
594*1fd5a2e1SPrashanth Swaminathan	/* set up registers for the routine that actually does the work */
595*1fd5a2e1SPrashanth Swaminathan	mr   r3, 11	/* go closure */
596*1fd5a2e1SPrashanth Swaminathan
597*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the result storage */
598*1fd5a2e1SPrashanth Swaminathan	addi r4, r1, 56
599*1fd5a2e1SPrashanth Swaminathan
600*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the saved gpr registers */
601*1fd5a2e1SPrashanth Swaminathan	addi r5, r1, 200
602*1fd5a2e1SPrashanth Swaminathan
603*1fd5a2e1SPrashanth Swaminathan	/* now load up the pointer to the saved fpr registers */
604*1fd5a2e1SPrashanth Swaminathan	addi r6, r1, 72
605*1fd5a2e1SPrashanth Swaminathan
606*1fd5a2e1SPrashanth Swaminathan	/* make the call */
607*1fd5a2e1SPrashanth Swaminathan	bl .ffi_go_closure_helper_DARWIN
608*1fd5a2e1SPrashanth Swaminathan	nop
609*1fd5a2e1SPrashanth Swaminathan
610*1fd5a2e1SPrashanth Swaminathan	b    .Ldoneclosure
611*1fd5a2e1SPrashanth SwaminathanLFE..1:
612*1fd5a2e1SPrashanth Swaminathan#endif
613*1fd5a2e1SPrashanth Swaminathan	.ef __LINE__
614*1fd5a2e1SPrashanth Swaminathan/* END(ffi_go_closure_ASM) */
615*1fd5a2e1SPrashanth Swaminathan
616*1fd5a2e1SPrashanth Swaminathan/* EH frame stuff.  */
617*1fd5a2e1SPrashanth Swaminathan
618*1fd5a2e1SPrashanth Swaminathan#define LR_REGNO		0x41		/* Link Register (65), see rs6000.md */
619*1fd5a2e1SPrashanth Swaminathan#ifdef __64BIT__
620*1fd5a2e1SPrashanth Swaminathan#define PTRSIZE			8
621*1fd5a2e1SPrashanth Swaminathan#define LOG2_PTRSIZE		3
622*1fd5a2e1SPrashanth Swaminathan#define CFA_OFFSET		0xf0,0x01	/* LEB128 240 */
623*1fd5a2e1SPrashanth Swaminathan#define FDE_ENCODING		0x1c		/* DW_EH_PE_pcrel|DW_EH_PE_sdata8 */
624*1fd5a2e1SPrashanth Swaminathan#define EH_DATA_ALIGN_FACT	0x78		/* LEB128 -8 */
625*1fd5a2e1SPrashanth Swaminathan#else
626*1fd5a2e1SPrashanth Swaminathan#define PTRSIZE			4
627*1fd5a2e1SPrashanth Swaminathan#define LOG2_PTRSIZE		2
628*1fd5a2e1SPrashanth Swaminathan#define CFA_OFFSET		0xb0,0x01	/* LEB128 176 */
629*1fd5a2e1SPrashanth Swaminathan#define FDE_ENCODING		0x1b		/* DW_EH_PE_pcrel|DW_EH_PE_sdata4 */
630*1fd5a2e1SPrashanth Swaminathan#define EH_DATA_ALIGN_FACT	0x7c		/* LEB128 -4 */
631*1fd5a2e1SPrashanth Swaminathan#endif
632*1fd5a2e1SPrashanth Swaminathan
633*1fd5a2e1SPrashanth Swaminathan	.csect	_unwind.ro_[RO],4
634*1fd5a2e1SPrashanth Swaminathan	.align	LOG2_PTRSIZE
635*1fd5a2e1SPrashanth Swaminathan	.globl	_GLOBAL__F_libffi_src_powerpc_aix_closure
636*1fd5a2e1SPrashanth Swaminathan_GLOBAL__F_libffi_src_powerpc_aix_closure:
637*1fd5a2e1SPrashanth SwaminathanLframe..1:
638*1fd5a2e1SPrashanth Swaminathan	.vbyte	4,LECIE..1-LSCIE..1	/* CIE Length */
639*1fd5a2e1SPrashanth SwaminathanLSCIE..1:
640*1fd5a2e1SPrashanth Swaminathan	.vbyte	4,0			/* CIE Identifier Tag */
641*1fd5a2e1SPrashanth Swaminathan	.byte	0x3			/* CIE Version */
642*1fd5a2e1SPrashanth Swaminathan	.byte	"zR"			/* CIE Augmentation */
643*1fd5a2e1SPrashanth Swaminathan	.byte	0
644*1fd5a2e1SPrashanth Swaminathan	.byte	0x1			/* uleb128 0x1; CIE Code Alignment Factor */
645*1fd5a2e1SPrashanth Swaminathan	.byte	EH_DATA_ALIGN_FACT	/* leb128 -4/-8; CIE Data Alignment Factor */
646*1fd5a2e1SPrashanth Swaminathan	.byte	LR_REGNO		/* CIE RA Column */
647*1fd5a2e1SPrashanth Swaminathan	.byte	0x1			/* uleb128 0x1; Augmentation size */
648*1fd5a2e1SPrashanth Swaminathan	.byte	FDE_ENCODING		/* FDE Encoding (pcrel|sdata4/8) */
649*1fd5a2e1SPrashanth Swaminathan	.byte	0xc			/* DW_CFA_def_cfa */
650*1fd5a2e1SPrashanth Swaminathan	.byte	0x1			/*     uleb128 0x1; Register r1 */
651*1fd5a2e1SPrashanth Swaminathan	.byte	0			/*     uleb128 0x0; Offset 0 */
652*1fd5a2e1SPrashanth Swaminathan	.align	LOG2_PTRSIZE
653*1fd5a2e1SPrashanth SwaminathanLECIE..1:
654*1fd5a2e1SPrashanth SwaminathanLSFDE..1:
655*1fd5a2e1SPrashanth Swaminathan	.vbyte	4,LEFDE..1-LASFDE..1	/* FDE Length */
656*1fd5a2e1SPrashanth SwaminathanLASFDE..1:
657*1fd5a2e1SPrashanth Swaminathan	.vbyte	4,LASFDE..1-Lframe..1	/* FDE CIE offset */
658*1fd5a2e1SPrashanth Swaminathan	.vbyte	PTRSIZE,LFB..0-$	/* FDE initial location */
659*1fd5a2e1SPrashanth Swaminathan	.vbyte	PTRSIZE,LFE..0-LFB..0	/* FDE address range */
660*1fd5a2e1SPrashanth Swaminathan	.byte	0			/* uleb128 0x0; Augmentation size */
661*1fd5a2e1SPrashanth Swaminathan	.byte	0x4			/* DW_CFA_advance_loc4 */
662*1fd5a2e1SPrashanth Swaminathan	.vbyte	4,LCFI..1-LCFI..0
663*1fd5a2e1SPrashanth Swaminathan	.byte	0xe			/* DW_CFA_def_cfa_offset */
664*1fd5a2e1SPrashanth Swaminathan	.byte	CFA_OFFSET		/*     uleb128 176/240 */
665*1fd5a2e1SPrashanth Swaminathan	.byte	0x4			/* DW_CFA_advance_loc4 */
666*1fd5a2e1SPrashanth Swaminathan	.vbyte	4,LCFI..0-LFB..0
667*1fd5a2e1SPrashanth Swaminathan	.byte	0x11			/* DW_CFA_offset_extended_sf */
668*1fd5a2e1SPrashanth Swaminathan	.byte	LR_REGNO		/*     uleb128 LR_REGNO; Register LR */
669*1fd5a2e1SPrashanth Swaminathan	.byte	0x7e			/*     leb128 -2; Offset -2 (8/16) */
670*1fd5a2e1SPrashanth Swaminathan	.align	LOG2_PTRSIZE
671*1fd5a2e1SPrashanth SwaminathanLEFDE..1:
672*1fd5a2e1SPrashanth SwaminathanLSFDE..2:
673*1fd5a2e1SPrashanth Swaminathan	.vbyte	4,LEFDE..2-LASFDE..2	/* FDE Length */
674*1fd5a2e1SPrashanth SwaminathanLASFDE..2:
675*1fd5a2e1SPrashanth Swaminathan	.vbyte	4,LASFDE..2-Lframe..1	/* FDE CIE offset */
676*1fd5a2e1SPrashanth Swaminathan	.vbyte	PTRSIZE,LFB..1-$	/* FDE initial location */
677*1fd5a2e1SPrashanth Swaminathan	.vbyte	PTRSIZE,LFE..1-LFB..1	/* FDE address range */
678*1fd5a2e1SPrashanth Swaminathan	.byte	0			/* uleb128 0x0; Augmentation size */
679*1fd5a2e1SPrashanth Swaminathan	.byte	0x4			/* DW_CFA_advance_loc4 */
680*1fd5a2e1SPrashanth Swaminathan	.vbyte	4,LCFI..3-LCFI..2
681*1fd5a2e1SPrashanth Swaminathan	.byte	0xe			/* DW_CFA_def_cfa_offset */
682*1fd5a2e1SPrashanth Swaminathan	.byte	CFA_OFFSET		/*     uleb128 176/240 */
683*1fd5a2e1SPrashanth Swaminathan	.byte	0x4			/* DW_CFA_advance_loc4 */
684*1fd5a2e1SPrashanth Swaminathan	.vbyte	4,LCFI..2-LFB..1
685*1fd5a2e1SPrashanth Swaminathan	.byte	0x11			/* DW_CFA_offset_extended_sf */
686*1fd5a2e1SPrashanth Swaminathan	.byte	LR_REGNO		/*     uleb128 LR_REGNO; Register LR */
687*1fd5a2e1SPrashanth Swaminathan	.byte	0x7e			/*     leb128 -2; Offset -2 (8/16) */
688*1fd5a2e1SPrashanth Swaminathan	.align	LOG2_PTRSIZE
689*1fd5a2e1SPrashanth SwaminathanLEFDE..2:
690*1fd5a2e1SPrashanth Swaminathan	.vbyte	4,0			/* End of FDEs */
691*1fd5a2e1SPrashanth Swaminathan
692*1fd5a2e1SPrashanth Swaminathan	.csect	.text[PR]
693*1fd5a2e1SPrashanth Swaminathan	.ref	_GLOBAL__F_libffi_src_powerpc_aix_closure	/* Prevents garbage collection by AIX linker */
694*1fd5a2e1SPrashanth Swaminathan
695