1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Chris Wilson <[email protected]>
25 *
26 */
27
28 /** @file gen3_linear_render_blits.c
29 *
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
32 *
33 * The goal is to simply ensure the basics work.
34 */
35
36 #include "igt.h"
37 #include <stdlib.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <fcntl.h>
41 #include <inttypes.h>
42 #include <errno.h>
43 #include <sys/stat.h>
44 #include <sys/time.h>
45 #include <sys/ioctl.h>
46 #include "drm.h"
47
48 #include "i915_reg.h"
49
50 #define WIDTH (512)
51 #define HEIGHT (512)
52
pack_float(float f)53 static inline uint32_t pack_float(float f)
54 {
55 union {
56 uint32_t dw;
57 float f;
58 } u;
59 u.f = f;
60 return u.dw;
61 }
62
fill_reloc(struct drm_i915_gem_relocation_entry * reloc,uint32_t offset,uint32_t handle,uint32_t read_domain,uint32_t write_domain)63 static uint32_t fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
64 uint32_t offset,
65 uint32_t handle,
66 uint32_t read_domain,
67 uint32_t write_domain)
68 {
69 reloc->target_handle = handle;
70 reloc->delta = 0;
71 reloc->offset = offset * sizeof(uint32_t);
72 reloc->presumed_offset = 0;
73 reloc->read_domains = read_domain;
74 reloc->write_domain = write_domain;
75
76 return reloc->presumed_offset + reloc->delta;
77 }
78
79 static void
render_copy(int fd,uint32_t dst,int dst_tiling,uint32_t src,int src_tiling,int use_fence)80 render_copy(int fd,
81 uint32_t dst, int dst_tiling,
82 uint32_t src, int src_tiling,
83 int use_fence)
84 {
85 uint32_t batch[1024], *b = batch;
86 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
87 struct drm_i915_gem_exec_object2 obj[3];
88 struct drm_i915_gem_execbuffer2 exec;
89 uint32_t handle;
90 uint32_t tiling_bits;
91
92 /* invariant state */
93 *b++ = (_3DSTATE_AA_CMD |
94 AA_LINE_ECAAR_WIDTH_ENABLE |
95 AA_LINE_ECAAR_WIDTH_1_0 |
96 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
97 *b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
98 IAB_MODIFY_ENABLE |
99 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
100 IAB_MODIFY_SRC_FACTOR |
101 (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) |
102 IAB_MODIFY_DST_FACTOR |
103 (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT));
104 *b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
105 *b++ = (0);
106 *b++ = (_3DSTATE_DFLT_SPEC_CMD);
107 *b++ = (0);
108 *b++ = (_3DSTATE_DFLT_Z_CMD);
109 *b++ = (0);
110 *b++ = (_3DSTATE_COORD_SET_BINDINGS |
111 CSB_TCB(0, 0) |
112 CSB_TCB(1, 1) |
113 CSB_TCB(2, 2) |
114 CSB_TCB(3, 3) |
115 CSB_TCB(4, 4) |
116 CSB_TCB(5, 5) |
117 CSB_TCB(6, 6) |
118 CSB_TCB(7, 7));
119 *b++ = (_3DSTATE_RASTER_RULES_CMD |
120 ENABLE_POINT_RASTER_RULE |
121 OGL_POINT_RASTER_RULE |
122 ENABLE_LINE_STRIP_PROVOKE_VRTX |
123 ENABLE_TRI_FAN_PROVOKE_VRTX |
124 LINE_STRIP_PROVOKE_VRTX(1) |
125 TRI_FAN_PROVOKE_VRTX(2) |
126 ENABLE_TEXKILL_3D_4D |
127 TEXKILL_4D);
128 *b++ = (_3DSTATE_MODES_4_CMD |
129 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
130 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
131 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
132 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
133 *b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
134 *b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
135 S4_LINE_WIDTH_ONE |
136 S4_CULLMODE_NONE |
137 S4_VFMT_XY);
138 *b++ = (0x00000000); /* Stencil. */
139 *b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
140 *b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
141 *b++ = (0);
142 *b++ = (0);
143 *b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
144 *b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
145 *b++ = (0);
146 *b++ = (_3DSTATE_STIPPLE);
147 *b++ = (0x00000000);
148 *b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
149
150 /* samler state */
151 if (use_fence) {
152 tiling_bits = MS3_USE_FENCE_REGS;
153 } else {
154 tiling_bits = 0;
155 if (src_tiling != I915_TILING_NONE)
156 tiling_bits = MS3_TILED_SURFACE;
157 if (src_tiling == I915_TILING_Y)
158 tiling_bits |= MS3_TILE_WALK;
159 }
160
161 #define TEX_COUNT 1
162 *b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
163 *b++ = ((1 << TEX_COUNT) - 1);
164 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
165 *b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 | tiling_bits |
166 (HEIGHT - 1) << MS3_HEIGHT_SHIFT |
167 (WIDTH - 1) << MS3_WIDTH_SHIFT);
168 *b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
169
170 *b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
171 *b++ = ((1 << TEX_COUNT) - 1);
172 *b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
173 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
174 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
175 *b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
176 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
177 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
178 *b++ = (0x00000000);
179
180 /* render target state */
181 if (use_fence) {
182 tiling_bits = BUF_3D_USE_FENCE;
183 } else {
184 tiling_bits = 0;
185 if (dst_tiling != I915_TILING_NONE)
186 tiling_bits = BUF_3D_TILED_SURFACE;
187 if (dst_tiling == I915_TILING_Y)
188 tiling_bits |= BUF_3D_TILE_WALK_Y;
189 }
190 *b++ = (_3DSTATE_BUF_INFO_CMD);
191 *b++ = (BUF_3D_ID_COLOR_BACK | tiling_bits | WIDTH*4);
192 *b = fill_reloc(r++, b-batch, dst,
193 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
194 b++;
195
196 *b++ = (_3DSTATE_DST_BUF_VARS_CMD);
197 *b++ = (COLR_BUF_ARGB8888 |
198 DSTORG_HORT_BIAS(0x8) |
199 DSTORG_VERT_BIAS(0x8));
200
201 /* draw rect is unconditional */
202 *b++ = (_3DSTATE_DRAW_RECT_CMD);
203 *b++ = (0x00000000);
204 *b++ = (0x00000000); /* ymin, xmin */
205 *b++ = (DRAW_YMAX(HEIGHT - 1) |
206 DRAW_XMAX(WIDTH - 1));
207 /* yorig, xorig (relate to color buffer?) */
208 *b++ = (0x00000000);
209
210 /* texfmt */
211 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
212 *b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
213 *b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
214 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
215 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
216 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
217 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
218 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
219
220 /* pixel shader */
221 *b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
222 /* decl FS_T0 */
223 *b++ = (D0_DCL |
224 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
225 REG_NR(FS_T0) << D0_NR_SHIFT |
226 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
227 *b++ = (0);
228 *b++ = (0);
229 /* decl FS_S0 */
230 *b++ = (D0_DCL |
231 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
232 (REG_NR(FS_S0) << D0_NR_SHIFT) |
233 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
234 *b++ = (0);
235 *b++ = (0);
236 /* texld(FS_OC, FS_S0, FS_T0 */
237 *b++ = (T0_TEXLD |
238 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
239 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
240 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
241 *b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
242 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
243 *b++ = (0);
244
245 *b++ = (PRIM3D_RECTLIST | (3*4 - 1));
246 *b++ = pack_float(WIDTH);
247 *b++ = pack_float(HEIGHT);
248 *b++ = pack_float(WIDTH);
249 *b++ = pack_float(HEIGHT);
250
251 *b++ = pack_float(0);
252 *b++ = pack_float(HEIGHT);
253 *b++ = pack_float(0);
254 *b++ = pack_float(HEIGHT);
255
256 *b++ = pack_float(0);
257 *b++ = pack_float(0);
258 *b++ = pack_float(0);
259 *b++ = pack_float(0);
260
261 *b++ = MI_BATCH_BUFFER_END;
262 if ((b - batch) & 1)
263 *b++ = 0;
264
265 igt_assert(b - batch <= 1024);
266 handle = gem_create(fd, 4096);
267 gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
268
269 igt_assert(r-reloc == 2);
270
271 tiling_bits = 0;
272 if (use_fence)
273 tiling_bits = EXEC_OBJECT_NEEDS_FENCE;
274
275 obj[0].handle = dst;
276 obj[0].relocation_count = 0;
277 obj[0].relocs_ptr = 0;
278 obj[0].alignment = 0;
279 obj[0].offset = 0;
280 obj[0].flags = tiling_bits;
281 obj[0].rsvd1 = 0;
282 obj[0].rsvd2 = 0;
283
284 obj[1].handle = src;
285 obj[1].relocation_count = 0;
286 obj[1].relocs_ptr = 0;
287 obj[1].alignment = 0;
288 obj[1].offset = 0;
289 obj[1].flags = tiling_bits;
290 obj[1].rsvd1 = 0;
291 obj[1].rsvd2 = 0;
292
293 obj[2].handle = handle;
294 obj[2].relocation_count = 2;
295 obj[2].relocs_ptr = (uintptr_t)reloc;
296 obj[2].alignment = 0;
297 obj[2].offset = 0;
298 obj[2].flags = 0;
299 obj[2].rsvd1 = obj[2].rsvd2 = 0;
300
301 exec.buffers_ptr = (uintptr_t)obj;
302 exec.buffer_count = 3;
303 exec.batch_start_offset = 0;
304 exec.batch_len = (b-batch)*sizeof(batch[0]);
305 exec.DR1 = exec.DR4 = 0;
306 exec.num_cliprects = 0;
307 exec.cliprects_ptr = 0;
308 exec.flags = 0;
309 i915_execbuffer2_set_context_id(exec, 0);
310 exec.rsvd2 = 0;
311
312 gem_execbuf(fd, &exec);
313
314 gem_close(fd, handle);
315 }
316
blt_copy(int fd,uint32_t dst,uint32_t src)317 static void blt_copy(int fd, uint32_t dst, uint32_t src)
318 {
319 uint32_t batch[1024], *b = batch;
320 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
321 struct drm_i915_gem_exec_object2 obj[3];
322 struct drm_i915_gem_execbuffer2 exec;
323 uint32_t handle;
324
325 *b++ = (XY_SRC_COPY_BLT_CMD |
326 XY_SRC_COPY_BLT_WRITE_ALPHA |
327 XY_SRC_COPY_BLT_WRITE_RGB | 6);
328 *b++ = 3 << 24 | 0xcc << 16 | WIDTH * 4;
329 *b++ = 0;
330 *b++ = HEIGHT << 16 | WIDTH;
331 *b = fill_reloc(r++, b-batch, dst,
332 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); b++;
333 *b++ = 0;
334 *b++ = WIDTH*4;
335 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_RENDER, 0); b++;
336
337 *b++ = MI_BATCH_BUFFER_END;
338 if ((b - batch) & 1)
339 *b++ = 0;
340
341 igt_assert(b - batch <= 1024);
342 handle = gem_create(fd, 4096);
343 gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
344
345 igt_assert(r-reloc == 2);
346
347 obj[0].handle = dst;
348 obj[0].relocation_count = 0;
349 obj[0].relocs_ptr = 0;
350 obj[0].alignment = 0;
351 obj[0].offset = 0;
352 obj[0].flags = EXEC_OBJECT_NEEDS_FENCE;
353 obj[0].rsvd1 = 0;
354 obj[0].rsvd2 = 0;
355
356 obj[1].handle = src;
357 obj[1].relocation_count = 0;
358 obj[1].relocs_ptr = 0;
359 obj[1].alignment = 0;
360 obj[1].offset = 0;
361 obj[1].flags = EXEC_OBJECT_NEEDS_FENCE;
362 obj[1].rsvd1 = 0;
363 obj[1].rsvd2 = 0;
364
365 obj[2].handle = handle;
366 obj[2].relocation_count = 2;
367 obj[2].relocs_ptr = (uintptr_t)reloc;
368 obj[2].alignment = 0;
369 obj[2].offset = 0;
370 obj[2].flags = 0;
371 obj[2].rsvd1 = obj[2].rsvd2 = 0;
372
373 exec.buffers_ptr = (uintptr_t)obj;
374 exec.buffer_count = 3;
375 exec.batch_start_offset = 0;
376 exec.batch_len = (b-batch)*sizeof(batch[0]);
377 exec.DR1 = exec.DR4 = 0;
378 exec.num_cliprects = 0;
379 exec.cliprects_ptr = 0;
380 exec.flags = 0;
381 i915_execbuffer2_set_context_id(exec, 0);
382 exec.rsvd2 = 0;
383
384 gem_execbuf(fd, &exec);
385
386 gem_close(fd, handle);
387 }
388
389
390 static void
copy(int fd,uint32_t dst,int dst_tiling,uint32_t src,int src_tiling)391 copy(int fd,
392 uint32_t dst, int dst_tiling,
393 uint32_t src, int src_tiling)
394 {
395 retry:
396 switch (random() % 3) {
397 case 0: render_copy(fd, dst, dst_tiling, src, src_tiling, 0); break;
398 case 1: render_copy(fd, dst, dst_tiling, src, src_tiling, 1); break;
399 case 2: if (dst_tiling == I915_TILING_Y || src_tiling == I915_TILING_Y)
400 goto retry;
401 blt_copy(fd, dst, src);
402 break;
403 }
404 }
405
406 static uint32_t
create_bo(int fd,uint32_t val,int tiling)407 create_bo(int fd, uint32_t val, int tiling)
408 {
409 uint32_t handle;
410 uint32_t *v;
411 int i;
412
413 handle = gem_create(fd, WIDTH*HEIGHT*4);
414 gem_set_tiling(fd, handle, tiling, WIDTH*4);
415
416 /* Fill the BO with dwords starting at val */
417 v = gem_mmap__gtt(fd, handle, WIDTH * HEIGHT * 4,
418 PROT_READ | PROT_WRITE);
419 gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
420 for (i = 0; i < WIDTH*HEIGHT; i++)
421 v[i] = val++;
422 munmap(v, WIDTH*HEIGHT*4);
423
424 return handle;
425 }
426
427 static void
check_bo(int fd,uint32_t handle,uint32_t val)428 check_bo(int fd, uint32_t handle, uint32_t val)
429 {
430 uint32_t *v;
431 int i;
432
433 v = gem_mmap__gtt(fd, handle, WIDTH * HEIGHT * 4, PROT_READ);
434 gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, 0);
435 for (i = 0; i < WIDTH*HEIGHT; i++) {
436 igt_assert_f(v[i] == val,
437 "Expected 0x%08x, found 0x%08x "
438 "at offset 0x%08x\n",
439 val, v[i], i * 4);
440 val++;
441 }
442 munmap(v, WIDTH*HEIGHT*4);
443 }
444
445 int count;
446
opt_handler(int opt,int opt_index,void * data)447 static int opt_handler(int opt, int opt_index, void *data)
448 {
449 switch (opt) {
450 case 'c':
451 count = atoi(optarg);
452 break;
453 default:
454 return IGT_OPT_HANDLER_ERROR;
455 }
456
457 return IGT_OPT_HANDLER_SUCCESS;
458 }
459
460 const char *help_str = " -c\tBuffer count\n";
461
462 igt_simple_main_args("c:", NULL, help_str, opt_handler, NULL)
463 {
464 uint32_t *handle, *tiling, *start_val;
465 uint32_t start = 0;
466 int i, fd;
467
468 fd = drm_open_driver(DRIVER_INTEL);
469
470 igt_require(IS_GEN3(intel_get_drm_devid(fd)));
471
472 if (count == 0)
473 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
474 igt_info("Using %d 1MiB buffers\n", count);
475 intel_require_memory(count, 1024*1024, CHECK_RAM);
476
477 handle = malloc(sizeof(uint32_t)*count*3);
478 tiling = handle + count;
479 start_val = tiling + count;
480
481 for (i = 0; i < count; i++) {
482 handle[i] = create_bo(fd, start, tiling[i] = i % 3);
483 start_val[i] = start;
484 start += 1024 * 1024 / 4;
485 }
486
487 igt_info("Verifying initialisation..."); fflush(stdout);
488 for (i = 0; i < count; i++)
489 check_bo(fd, handle[i], start_val[i]);
490 igt_info("done\n");
491
492 igt_info("Cyclic blits, forward..."); fflush(stdout);
493 for (i = 0; i < count * 32; i++) {
494 int src = i % count;
495 int dst = (i + 1) % count;
496
497 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
498 start_val[dst] = start_val[src];
499 }
500 igt_info("verifying..."); fflush(stdout);
501 for (i = 0; i < count; i++)
502 check_bo(fd, handle[i], start_val[i]);
503 igt_info("done\n");
504
505 igt_info("Cyclic blits, backward..."); fflush(stdout);
506 for (i = 0; i < count * 32; i++) {
507 int src = (i + 1) % count;
508 int dst = i % count;
509
510 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
511 start_val[dst] = start_val[src];
512 }
513 igt_info("verifying..."); fflush(stdout);
514 for (i = 0; i < count; i++)
515 check_bo(fd, handle[i], start_val[i]);
516 igt_info("done\n");
517
518 igt_info("Random blits..."); fflush(stdout);
519 for (i = 0; i < count * 32; i++) {
520 int src = random() % count;
521 int dst = random() % count;
522
523 while (src == dst)
524 dst = random() % count;
525
526 copy(fd, handle[dst], tiling[dst], handle[src], tiling[src]);
527 start_val[dst] = start_val[src];
528 }
529 igt_info("verifying..."); fflush(stdout);
530 for (i = 0; i < count; i++)
531 check_bo(fd, handle[i], start_val[i]);
532 igt_info("done\n");
533 }
534