1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Chris Wilson <[email protected]>
25 *
26 */
27
28 #include "igt.h"
29 #include <unistd.h>
30 #include <stdlib.h>
31 #include <stdint.h>
32 #include <stdio.h>
33 #include <string.h>
34 #include <fcntl.h>
35 #include <inttypes.h>
36 #include <errno.h>
37 #include <sys/stat.h>
38 #include <sys/ioctl.h>
39 #include <sys/time.h>
40 #include "drm.h"
41 #include "igt_sysfs.h"
42
43 #define OBJECT_SIZE 16384
44
45 #define COPY_BLT_CMD (2<<29|0x53<<22|0x6)
46 #define BLT_WRITE_ALPHA (1<<21)
47 #define BLT_WRITE_RGB (1<<20)
48 #define BLT_SRC_TILED (1<<15)
49 #define BLT_DST_TILED (1<<11)
50
51 #define LOCAL_I915_EXEC_NO_RELOC (1<<11)
52 #define LOCAL_I915_EXEC_HANDLE_LUT (1<<12)
53
gem_linear_blt(int fd,uint32_t * batch,uint32_t src,uint32_t dst,uint32_t length,struct drm_i915_gem_relocation_entry * reloc)54 static int gem_linear_blt(int fd,
55 uint32_t *batch,
56 uint32_t src,
57 uint32_t dst,
58 uint32_t length,
59 struct drm_i915_gem_relocation_entry *reloc)
60 {
61 uint32_t *b = batch;
62 int height = length / (16 * 1024);
63
64 igt_assert_lte(height, 1 << 16);
65
66 if (height) {
67 int i = 0;
68 b[i++] = COPY_BLT_CMD | BLT_WRITE_ALPHA | BLT_WRITE_RGB;
69 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
70 b[i-1]+=2;
71 b[i++] = 0xcc << 16 | 1 << 25 | 1 << 24 | (16*1024);
72 b[i++] = 0;
73 b[i++] = height << 16 | (4*1024);
74 b[i++] = 0;
75 reloc->offset = (b-batch+4) * sizeof(uint32_t);
76 reloc->delta = 0;
77 reloc->target_handle = dst;
78 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
79 reloc->write_domain = I915_GEM_DOMAIN_RENDER;
80 reloc->presumed_offset = 0;
81 reloc++;
82 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
83 b[i++] = 0; /* FIXME */
84
85 b[i++] = 0;
86 b[i++] = 16*1024;
87 b[i++] = 0;
88 reloc->offset = (b-batch+7) * sizeof(uint32_t);
89 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
90 reloc->offset += sizeof(uint32_t);
91 reloc->delta = 0;
92 reloc->target_handle = src;
93 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
94 reloc->write_domain = 0;
95 reloc->presumed_offset = 0;
96 reloc++;
97 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
98 b[i++] = 0; /* FIXME */
99
100 b += i;
101 length -= height * 16*1024;
102 }
103
104 if (length) {
105 int i = 0;
106 b[i++] = COPY_BLT_CMD | BLT_WRITE_ALPHA | BLT_WRITE_RGB;
107 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
108 b[i-1]+=2;
109 b[i++] = 0xcc << 16 | 1 << 25 | 1 << 24 | (16*1024);
110 b[i++] = height << 16;
111 b[i++] = (1+height) << 16 | (length / 4);
112 b[i++] = 0;
113 reloc->offset = (b-batch+4) * sizeof(uint32_t);
114 reloc->delta = 0;
115 reloc->target_handle = dst;
116 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
117 reloc->write_domain = I915_GEM_DOMAIN_RENDER;
118 reloc->presumed_offset = 0;
119 reloc++;
120 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
121 b[i++] = 0; /* FIXME */
122
123 b[i++] = height << 16;
124 b[i++] = 16*1024;
125 b[i++] = 0;
126 reloc->offset = (b-batch+7) * sizeof(uint32_t);
127 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
128 reloc->offset += sizeof(uint32_t);
129 reloc->delta = 0;
130 reloc->target_handle = src;
131 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
132 reloc->write_domain = 0;
133 reloc->presumed_offset = 0;
134 reloc++;
135 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
136 b[i++] = 0; /* FIXME */
137
138 b += i;
139 }
140
141 b[0] = MI_BATCH_BUFFER_END;
142 b[1] = 0;
143
144 return (b+2 - batch) * sizeof(uint32_t);
145 }
146
elapsed(const struct timeval * start,const struct timeval * end,int loop)147 static double elapsed(const struct timeval *start,
148 const struct timeval *end,
149 int loop)
150 {
151 return (1e6*(end->tv_sec - start->tv_sec) + (end->tv_usec - start->tv_usec))/loop;
152 }
153
bytes_per_sec(char * buf,double v)154 static const char *bytes_per_sec(char *buf, double v)
155 {
156 const char *order[] = {
157 "",
158 "KiB",
159 "MiB",
160 "GiB",
161 "TiB",
162 "PiB",
163 NULL,
164 }, **o = order;
165
166 while (v > 1024 && o[1]) {
167 v /= 1024;
168 o++;
169 }
170 sprintf(buf, "%.1f%s/s", v, *o);
171 return buf;
172 }
173
dcmp(const void * A,const void * B)174 static int dcmp(const void *A, const void *B)
175 {
176 const double *a = A, *b = B;
177 if (*a < *b)
178 return -1;
179 else if (*a > *b)
180 return 1;
181 else
182 return 0;
183 }
184
run(int fd,int object_size,bool dumb)185 static void run(int fd, int object_size, bool dumb)
186 {
187 struct drm_i915_gem_execbuffer2 execbuf;
188 struct drm_i915_gem_exec_object2 exec[3];
189 struct drm_i915_gem_relocation_entry reloc[4];
190 uint32_t buf[20];
191 uint32_t handle, src, dst;
192 int len, count;
193 int ring;
194
195 if (dumb)
196 handle = kmstest_dumb_create(fd, 32, 32, 32, NULL, NULL);
197 else
198 handle = gem_create(fd, 4096);
199
200 src = gem_create(fd, object_size);
201 dst = gem_create(fd, object_size);
202
203 len = gem_linear_blt(fd, buf, 0, 1, object_size, reloc);
204 gem_write(fd, handle, 0, buf, len);
205
206 memset(exec, 0, sizeof(exec));
207 exec[0].handle = src;
208 exec[1].handle = dst;
209
210 exec[2].handle = handle;
211 if (intel_gen(intel_get_drm_devid(fd)) >= 8)
212 exec[2].relocation_count = len > 56 ? 4 : 2;
213 else
214 exec[2].relocation_count = len > 40 ? 4 : 2;
215 exec[2].relocs_ptr = to_user_pointer(reloc);
216
217 ring = 0;
218 if (HAS_BLT_RING(intel_get_drm_devid(fd)))
219 ring = I915_EXEC_BLT;
220
221 memset(&execbuf, 0, sizeof(execbuf));
222 execbuf.buffers_ptr = to_user_pointer(exec);
223 execbuf.buffer_count = 3;
224 execbuf.batch_len = len;
225 execbuf.flags = ring;
226 execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
227 execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
228
229 if (__gem_execbuf(fd, &execbuf)) {
230 len = gem_linear_blt(fd, buf, src, dst, object_size, reloc);
231 igt_assert(len == execbuf.batch_len);
232 gem_write(fd, handle, 0, buf, len);
233 execbuf.flags = ring;
234 gem_execbuf(fd, &execbuf);
235 }
236 gem_sync(fd, handle);
237
238 for (count = 1; count <= 1<<12; count <<= 1) {
239 struct timeval start, end;
240 const int reps = 9;
241 double t[reps], sum;
242 int n;
243
244 for (n = 0; n < reps; n++) {
245 gettimeofday(&start, NULL);
246 for (int loop = 0; loop < count; loop++)
247 gem_execbuf(fd, &execbuf);
248 gem_sync(fd, handle);
249 gettimeofday(&end, NULL);
250 t[n] = elapsed(&start, &end, count);
251 }
252 qsort(t, n, sizeof(double), dcmp);
253 sum = 0;
254 for (n = 2; n < reps - 2; n++)
255 sum += t[n];
256 sum /= reps - 4;
257 igt_info("Time to blt %d bytes x %6d: %7.3fµs, %s\n",
258 object_size, count, sum,
259 bytes_per_sec((char *)buf, object_size/sum*1e6));
260 fflush(stdout);
261 }
262 gem_close(fd, handle);
263 }
264
set_auto_freq(int sysfs)265 static void set_auto_freq(int sysfs)
266 {
267 int min = igt_sysfs_get_u32(sysfs, "gt_RPn_freq_mhz");
268 int max = igt_sysfs_get_u32(sysfs, "gt_RP0_freq_mhz");
269 if (max <= min)
270 return;
271
272 igt_debug("Setting min to %dMHz, and max to %dMHz\n", min, max);
273 igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min);
274 igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", max);
275 }
276
set_min_freq(int sysfs)277 static void set_min_freq(int sysfs)
278 {
279 int min = igt_sysfs_get_u32(sysfs, "gt_RPn_freq_mhz");
280 igt_require(min > 0);
281 igt_debug("Setting min/max to %dMHz\n", min);
282 igt_require(igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min) &&
283 igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", min));
284 }
285
set_max_freq(int sysfs)286 static void set_max_freq(int sysfs)
287 {
288 int max = igt_sysfs_get_u32(sysfs, "gt_RP0_freq_mhz");
289 igt_require(max > 0);
290 igt_debug("Setting min/max to %dMHz\n", max);
291 igt_require(igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", max) &&
292 igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", max));
293 }
294
295
296 igt_main
297 {
298 const struct {
299 const char *suffix;
300 void (*func)(int);
301 } rps[] = {
302 { "", set_auto_freq },
303 { "-min", set_min_freq },
304 { "-max", set_max_freq },
305 { NULL, NULL },
306 }, *r;
307 int min = -1, max = -1;
308 int fd, sysfs;
309
310 igt_skip_on_simulation();
311
312 igt_fixture {
313 fd = drm_open_driver(DRIVER_INTEL);
314 igt_require_gem(fd);
315
316 sysfs = igt_sysfs_open(fd);
317 igt_require(sysfs >= 0);
318
319 min = igt_sysfs_get_u32(sysfs, "gt_min_freq_mhz");
320 max = igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz");
321 }
322
323 for (r = rps; r->suffix; r++) {
324 igt_fixture r->func(sysfs);
325
326 igt_subtest_f("cold%s", r->suffix)
327 run(fd, OBJECT_SIZE, false);
328
329 igt_subtest_f("normal%s", r->suffix)
330 run(fd, OBJECT_SIZE, false);
331
332 igt_subtest_f("dumb-buf%s", r->suffix)
333 run(fd, OBJECT_SIZE, true);
334 }
335
336 igt_fixture {
337 if (min > 0)
338 igt_sysfs_set_u32(sysfs, "gt_min_freq_mhz", min);
339 if (max > 0)
340 igt_sysfs_set_u32(sysfs, "gt_max_freq_mhz", max);
341
342 close(sysfs);
343 close(fd);
344 }
345 }
346