1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <[email protected]>
25 *
26 */
27
28 /*
29 * Testcase: Test the CS prefetch behaviour on batches
30 *
31 * Historically the batch prefetcher doesn't check whether it's crossing page
32 * boundaries and likes to throw up when it gets a pagefault in return for his
33 * over-eager behaviour. Check for this.
34 *
35 * This test for a bug where we've failed to plug a scratch pte entry into the
36 * very last gtt pte.
37 */
38 #include "igt.h"
39
40 IGT_TEST_DESCRIPTION("Test the CS prefetch behaviour on batches.");
41
42 #define BATCH_SIZE 4096
43
44 struct shadow {
45 uint32_t handle;
46 struct drm_i915_gem_relocation_entry reloc;
47 };
48
setup(int fd,int gen,struct shadow * shadow)49 static void setup(int fd, int gen, struct shadow *shadow)
50 {
51 uint32_t buf[16];
52 int i;
53
54 shadow->handle = gem_create(fd, 4096);
55
56 i = 0;
57 buf[i++] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
58 if (gen >= 8) {
59 buf[i++] = BATCH_SIZE - sizeof(uint32_t);
60 buf[i++] = 0;
61 } else if (gen >= 4) {
62 buf[i++] = 0;
63 buf[i++] = BATCH_SIZE - sizeof(uint32_t);
64 } else {
65 buf[i-1]--;
66 buf[i++] = BATCH_SIZE - sizeof(uint32_t);
67 }
68 buf[i++] = MI_BATCH_BUFFER_END;
69 buf[i++] = MI_BATCH_BUFFER_END;
70 gem_write(fd, shadow->handle, 0, buf, sizeof(buf));
71
72 memset(&shadow->reloc, 0, sizeof(shadow->reloc));
73 if (gen >= 8 || gen < 4)
74 shadow->reloc.offset = sizeof(uint32_t);
75 else
76 shadow->reloc.offset = 2*sizeof(uint32_t);
77 shadow->reloc.delta = BATCH_SIZE - sizeof(uint32_t);
78 shadow->reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
79 shadow->reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
80 }
81
can_test_ring(unsigned ring)82 static void can_test_ring(unsigned ring)
83 {
84 int master = drm_open_driver_master(DRIVER_INTEL);
85 int fd = drm_open_driver(DRIVER_INTEL);
86
87 /* Dance to avoid dying with master open */
88 close(master);
89 igt_require_gem(fd);
90 gem_require_ring(fd, ring);
91 igt_require(gem_can_store_dword(fd, ring));
92 close(fd);
93 }
94
test_ring(unsigned ring)95 static void test_ring(unsigned ring)
96 {
97 struct drm_i915_gem_execbuffer2 execbuf;
98 struct drm_i915_gem_exec_object2 obj[2];
99 struct shadow shadow;
100 uint64_t i, count;
101 int fd, gen;
102
103 can_test_ring(ring);
104
105 fd = drm_open_driver_master(DRIVER_INTEL);
106 gen = intel_gen(intel_get_drm_devid(fd));
107 setup(fd, gen, &shadow);
108
109 count = gem_aperture_size(fd) / BATCH_SIZE;
110 intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
111 /* Fill the entire gart with batches and run them. */
112 memset(obj, 0, sizeof(obj));
113 obj[1].handle = shadow.handle;
114 obj[1].relocs_ptr = to_user_pointer(&shadow.reloc);
115 obj[1].relocation_count = 1;
116
117 memset(&execbuf, 0, sizeof(execbuf));
118 execbuf.buffers_ptr = to_user_pointer(obj);
119 execbuf.flags = ring;
120 if (gen < 6)
121 execbuf.flags |= I915_EXEC_SECURE;
122
123 for (i = 0; i < count; i++) {
124 /* Create the new batch using the GPU */
125 obj[0].handle = gem_create(fd, BATCH_SIZE);
126 shadow.reloc.target_handle = obj[0].handle;
127 execbuf.buffer_count = 2;
128 gem_execbuf(fd, &execbuf);
129
130 /* ...then execute the new batch */
131 execbuf.buffer_count = 1;
132 gem_execbuf(fd, &execbuf);
133
134 /* ...and leak the handle to consume the GTT */
135 }
136
137 close(fd);
138 }
139
140 igt_main
141 {
142 const struct intel_execution_engine *e;
143
144 igt_skip_on_simulation();
145
146 for (e = intel_execution_engines; e->name; e++)
147 igt_subtest_f("%s", e->name)
148 test_ring(e->exec_id | e->flags);
149 }
150