1/* -*- mode:c -*- 2 * Copyright 2016 The ChromiumOS Authors 3 * Use of this source code is governed by a BSD-style license that can be 4 * found in the LICENSE file. 5 */ 6 7/* 8 * This file describes GPIO mapping for the cr50 code running on the H1 chip. 9 * 10 * For the purposes of this file H1 core has the following logical and 11 * physical items and properties: 12 * 13 * - 32 internal GPIOs, which are split into two ports of 16 bits each. 14 * Ports' architecture and programmig is described in "ARM Cortex-M System 15 * Design Kit TRM" DDIO47B. 16 * 17 * - a set of modules - SPI and I2C controller and peripheral interfaces, 18 * UARTs, interrupt controller, etc. 19 * 20 * - 28 pins on the package named DIOA0..14, DIOB0..7 and DIOM0..4 21 * 22 * - a PINMUX - a unit which allows to interconnect objects from the three 23 * groups listed above. Note that some modules are attached to some pins 24 * directly, so in case those modules are used the pins should not be 25 * connected by PINMUX to any other outputs. 26 * 27 * The below macros are somewhat misleading (apparently for historical 28 * reasons), as PIN(p, b) component in fact refers not to the external pin, 29 * but to the GPIO (bit b on port p), where bit is in 0..15 range, and port is 30 * in 0..1 range. 31 * 32 * To describe routing of an external signal two macro instantiations are 33 * required: 34 * 35 * The GPIO_INT() or GPIO() macro assigns the signal a name and assigns it to 36 * the internal GPIO port, (again, defining the port using the PIN(port, bit) 37 * component of the macro invocation). GPIO_INT definitions assign their 38 * respective signals to interrupts and ISRs. 39 * 40 * The PINMUX macro assigns the previously defined GPIO to another object, 41 * most commonly to an external pin, but possibly to some internal component. 42 */ 43 44/* Declare symbolic names for all the GPIOs that we care about. 45 * Note: Those with interrupt handlers must be declared first. */ 46 47/* 48 * A manually maintained tally of all GPIO ports configured in this file. 49 * 50 * GPIO0.0 int_ap_l 51 * GPIO0.1 ec_flash_select 52 * GPIO0.2 ap_flash_select 53 * GPIO0.3 DIOM4 used for physical presence 54 * GPIO0.4 sys_rst_l_out 55 * GPIO0.5 ccd_mode_l 56 * GPIO0.6 batt_pres_l 57 * GPIO0.7 spi_mosi 58 * GPIO0.8 spi_clk 59 * GPIO0.9 spi_cs_l 60 * GPIO0.10 diob4 61 * GPIO0.11 en_pp3300_ina 62 * GPIO0.12 i2c_scl_ina 63 * GPIO0.13 i2c_sda_ina 64 * GPIO0.14 i2cp_sda poll 65 * GPIO0.15 ec_tx_cr50_rx_out 66 * GPIO1.0 tpm_rst_l 67 * GPIO1.1 detect_ap_uart 68 * GPIO1.2 detect_ec_uart 69 * GPIO1.3 detect_servo 70 * GPIO1.4 detect_tpm_rst_asserted 71 * GPIO1.5 unwedge_i2cp_scl 72 * GPIO1.6 monitor_i2cp_sda 73 * GPIO1.7 ec_packet_mode_en 74 * GPIO1.8 ec_packet_mode_dis 75 * GPIO1.10 rec_lid_switch 76 * GPIO1.11 ec_tx_cr50_rx_in 77 * GPIO1.12 strap_a0 78 * GPIO1.13 strap_a1 79 * GPIO1.14 strap_b0 80 * GPIO1.15 strap_b1 81 */ 82/*****************************************************************************/ 83/* INTERRUPT GPIOs - interrupts processed in chip/g/gpio.c */ 84/* 85 * The system reset signal can be from two different pins depending on what the 86 * board type is. One board uses plt_rst_l (diom3) and the other board type uses 87 * sys_rst_l (diom0) to detect a warm reset. The pin is selected based on the 88 * board properties in board.c 89 * 90 * On both boards sys_rst_l is used as an output to trigger warm resets. The ARM 91 * core can't trigger an interrupt if it's driving it as an output so we attach 92 * two internal GPIOs to the same pad if sys_rst_l is also being used to detect 93 * system resets. 94 */ 95GPIO_INT(TPM_RST_L, PIN(1, 0), GPIO_INT_RISING, tpm_rst_deasserted) 96GPIO_INT(DETECT_AP_UART, PIN(1, 1), GPIO_INT_HIGH, ap_detect_asserted) 97GPIO_INT(DETECT_EC_UART, PIN(1, 2), GPIO_INT_HIGH, ec_detect_asserted) 98/* 99 * DETECT_SERVO and EC_TX_CR50_RX pins must NOT be changed without also changing 100 * the pinmux_regval fields in the bitbang_config in board.c. The pinmux values 101 * in the config assume the pin definitions here. 102 */ 103GPIO_INT(DETECT_SERVO, PIN(1, 3), GPIO_INT_HIGH | GPIO_PULL_DOWN, 104 servo_detect_asserted) 105/* 106 * Whan TPM_RST_L is asserted, the AP is in reset. Use this for detecting when 107 * the AP is off. 108 */ 109GPIO_INT(DETECT_TPM_RST_L_ASSERTED, PIN(1, 4), GPIO_INT_FALLING, 110 tpm_rst_asserted) 111 112/* 113 * A GPIO to sample the current state of the I2CP SDA line, allowing to detect 114 * the 'wedged I2C bus' condition. 115 * 116 * Also, it works to detect an I2C transaction during extended INT_AP_L 117 * assertion. 118 */ 119GPIO_INT(MONITOR_I2CP_SDA, PIN(1, 6), GPIO_INT_LOW, i2cp_sda_isr) 120 121/* 122 * These GPIOs are to enable or disable EC-CR50 communication. 123 * NOTE: If these are changed, you must update the information in board.c 124 * and ec_comm.c 125 */ 126GPIO_INT(EC_PACKET_MODE_EN, PIN(1, 7), GPIO_INT_RISING, ec_comm_packet_mode_en) 127GPIO_INT(EC_PACKET_MODE_DIS, PIN(1, 8), GPIO_INT_FALLING, 128 ec_comm_packet_mode_dis) 129 130/* 131 * Generic pulled up input used for physical presence indication on some 132 * devices. 133 */ 134GPIO_INT(DIOM4, PIN(0, 3), GPIO_INT_RISING, diom4_deasserted) 135 136/*****************************************************************************/ 137/* NON STANDARD INTERRUPT GPIOs - handlers defined and configured in board.c */ 138/* 139 * This signal is used as an interrupt for uart bitbang. This is setup manually 140 * in board.c instead of using chip/g/gpio.c, so the interrupts can be processed 141 * more quickly. This increases the max bitbang programming speed. 142 * 143 * If this gpio is changed, you must update the information in board.c. 144 */ 145GPIO(EC_TX_CR50_RX, PIN(1, 11), GPIO_INPUT) 146 147/*****************************************************************************/ 148/* GPIOs */ 149/* Pull this low to interrupt the AP */ 150GPIO(INT_AP_L, PIN(0, 0), GPIO_OUT_HIGH) 151 152/* 153 * Use these to take over the AP & EC flash (only when AP & EC are off!) 154 * Disable sleep when they're set to 1. 155 */ 156GPIO(EC_FLASH_SELECT, PIN(0, 1), GPIO_OUT_LOW | GPIO_SLEEP_DIS_HIGH) 157/* 158 * If this gpio is changed, you must update the AP_FLASH_SELECT pinmux 159 * setup in board.c accordingly. 160 */ 161GPIO(AP_FLASH_SELECT, PIN(0, 2), GPIO_OUT_LOW | GPIO_SLEEP_DIS_HIGH) 162 163/* 164 * Pull this low to reset the AP. (We reset the EC with the RBOX.) 165 * This is pseudo open drain. 166 */ 167GPIO(SYS_RST_L_OUT, PIN(0, 4), GPIO_ODR_HIGH) 168 169/* 170 * Indicate to EC when CCD is enabled. EC can pull this down too, to tell us if 171 * it decided instead. 172 * This is pseudo open drain. 173 */ 174GPIO(CCD_MODE_L, PIN(0, 5), GPIO_ODR_HIGH | GPIO_PULL_UP) 175 176/* Battery present signal is active low */ 177GPIO(BATT_PRES_L, PIN(0, 6), GPIO_INPUT) 178 179/* GPIOs used to tristate the SPI bus */ 180GPIO(SPI_MOSI, PIN(0, 7), GPIO_INPUT | GPIO_PULL_DOWN) 181GPIO(SPI_CLK, PIN(0, 8), GPIO_INPUT | GPIO_PULL_DOWN) 182GPIO(SPI_CS_L, PIN(0, 9), GPIO_INPUT) 183 184/* Used during *chip* factory process. */ 185GPIO(DIOB4, PIN(0, 10), GPIO_INPUT | GPIO_PULL_DOWN) 186 187/* 188 * Used to assert lid open or recovery switch with ccd. This signal is 189 * guaranteed to have an external pull-up. The pin is connected to the gpio in 190 * board.c. If the gpio number changes, it needs to be updated in board.c. 191 */ 192GPIO(CCD_REC_LID_SWITCH, PIN(1, 10), GPIO_ODR_HIGH | GPIO_INPUT) 193 194/* GPIOs used for Cr50 strapping options */ 195GPIO(STRAP_A0, PIN(1, 12), GPIO_INPUT) 196GPIO(STRAP_A1, PIN(1, 13), GPIO_INPUT) 197GPIO(STRAP_B0, PIN(1, 14), GPIO_INPUT) 198GPIO(STRAP_B1, PIN(1, 15), GPIO_INPUT) 199 200GPIO(UNWEDGE_I2CP_SCL, PIN(1, 5), GPIO_OUT_HIGH) 201 202/* 203 * If you change the names of EN_PP3300_INA_L, I2C_SCL_INA, or I2C_SDA_INA, 204 * you also need to update the usage in closed_source_set1.c 205 */ 206/* Control the load switch powering the INA 3.3V rail */ 207GPIO(EN_PP3300_INA_L, PIN(0, 11), GPIO_ODR_HIGH) 208/* GPIOs used for I2CC pins for INAs */ 209GPIO(I2C_SCL_INA, PIN(0, 12), GPIO_INPUT) 210GPIO(I2C_SDA_INA, PIN(0, 13), GPIO_INPUT) 211 212/* 213 * Use this to poll the state of the I2CP SDA line. Note that this is not 214 * necessary if SPI interface is used to communicate with the AP, if needed, 215 * this GPIO could be reclaimed in that case. 216 * 217 * Actual attachment of this GPIO to the SDA line happens in board.c only when 218 * I2CP interface is required. Should this GPIO ever change, the code setting 219 * up the pinmux in board.c will have to change as well. 220 */ 221GPIO(I2CP_SDA, PIN(0, 14), GPIO_INPUT) 222/* 223 * Fake open drain on EC_TX_CR50_RX_OUT. When asserted, the signal can be used 224 * to enable UART programming mode on the EC. The signal needs to fake open 225 * drain so it can still be used as the cr50 rx signal when it is deasserted. 226 * 227 * Disable sleep when cr50 sets it to 0. 228 */ 229GPIO(EC_TX_CR50_RX_OUT, PIN(0, 15), GPIO_ODR_HIGH | GPIO_SLEEP_DIS_LOW) 230 231/* 232 * ENTERING_RW is not a GPIO in H1, but an input pin to RBOX module. 233 * However, we declare it as 'UNIMPLEMENTED' to avoid a compile error in 234 * common/system.c. 235 */ 236UNIMPLEMENTED(ENTERING_RW) 237 238/* 239 * If we are included by generic GPIO code that doesn't know about the PINMUX 240 * macro we need to provide an empty definition so that the invocations don't 241 * interfere with other GPIO processing. 242 */ 243#ifndef PINMUX 244#define PINMUX(...) 245#endif 246 247/* GPIOs - mark outputs as inputs too, to read back from the driven pad */ 248PINMUX(GPIO(INT_AP_L), A5, DIO_INPUT) 249 250PINMUX(GPIO(DIOM4), M4, DIO_INPUT) 251 252PINMUX(GPIO(EC_FLASH_SELECT), B2, DIO_INPUT) 253PINMUX(GPIO(MONITOR_I2CP_SDA), A1, DIO_INPUT) 254 255/* 256 * Update closed_source_set1.c if pinmux for EN_PP3300_INA_L is changed or 257 * removed. 258 */ 259PINMUX(GPIO(EN_PP3300_INA_L), B7, DIO_INPUT) 260PINMUX(GPIO(SYS_RST_L_OUT), M0, DIO_INPUT) 261PINMUX(GPIO(CCD_MODE_L), M1, DIO_INPUT) 262PINMUX(GPIO(BATT_PRES_L), M2, 0) 263/* 264 * Update closed_source_set1.c if pinmux for I2C_SCL_INA or I2C_SDA_INA is 265 * changed or removed. 266 */ 267PINMUX(GPIO(I2C_SCL_INA), B0, DIO_INPUT) 268PINMUX(GPIO(I2C_SDA_INA), B1, DIO_INPUT) 269/* UARTs */ 270PINMUX(FUNC(UART0_TX), A0, DIO_OUTPUT) /* Cr50 console */ 271PINMUX(FUNC(UART0_RX), A13, DIO_INPUT | DIO_WAKE_LOW) 272/* 273 * UART1_TX and UART2_TX are configured in usart.c. They are not set as outputs 274 * here in order to avoid interfering with servo. They can be controlled using 275 * the 'uart' console command. 276 * UART1_TX = DIOA7 AP console 277 * UART2_TX = DIOB5 EC console 278 */ 279PINMUX(FUNC(UART1_RX), A3, DIO_INPUT) /* AP console */ 280PINMUX(FUNC(UART2_RX), B6, DIO_INPUT) /* EC console */ 281/* 282 * Monitor UART RX/TX signals to detect state changes on the EC, AP, and servo. 283 * 284 * The idle state of the RX signals when the AP or EC are powered on is high. 285 * When they are not powered, the signals will remain low. When servo is 286 * connected it drives the TX signals high. The servo TX signals are wired 287 * to cr50's. Because the two device TX signals are directly wired together, 288 * driving the cr50 uart TX at the same time as servo is driving those pins may 289 * damage both servo and cr50. 290 */ 291PINMUX(GPIO(DETECT_AP_UART), A3, DIO_INPUT) 292PINMUX(GPIO(DETECT_EC_UART), B6, DIO_INPUT) 293PINMUX(GPIO(EC_TX_CR50_RX), B6, DIO_INPUT) 294PINMUX(GPIO(EC_TX_CR50_RX_OUT), B6, DIO_INPUT) 295PINMUX(GPIO(DETECT_SERVO), B5, DIO_INPUT) 296 297/* 298 * I2CP pins are bi-directional and would be configured here as shown. However, 299 * A1 is also used as a strapping option GPIO input which is configured 300 * above. If a board is configured (via the strapping pins) to support the I2CP 301 * driver, then the connection of A1 and A9 to/from the I2C0_SDA and I2C0_SCL 302 * lines is done in the function i2cp_set_pinmux() which lives in board.c. 303 * 304 * PINMUX(FUNC(I2C0_SCL), A9, DIO_INPUT) 305 * PINMUX(FUNC(I2C0_SDA), A1, DIO_INPUT) 306*/ 307 308/* 309 * Both SPI controller and peripheral buses are wired directly to specific pads 310 * 311 * If CONFIG_SPP is defined, these pads are used: 312 * DIOA2 = SPS_MOSI (input) 313 * DIOA6 = SPS_CLK (input) 314 * DIOA10 = SPS_MISO (output) 315 * DIOA12 = SPS_CS_L (input) 316 * The digital inputs are enabled in spp.c 317 * 318 * If CONFIG_SPI_CONTROLLER is defined, these pads are used: 319 * DIOA4 = SPI_MOSI (output) 320 * DIOA8 = SPI_CLK (output) 321 * DIOA11 = SPI_MISO (input) 322 * DIOA14 = SPI_CS_L (output) 323 * The pads are only connected to the module outputs when SPI is enabled to 324 * avoid interfering with other things on the board. 325 * Note: Double-check to be sure these are configured in spi_controller.c 326 */ 327PINMUX(GPIO(SPI_MOSI), A4, DIO_OUTPUT) 328PINMUX(GPIO(SPI_CLK), A8, DIO_OUTPUT) 329PINMUX(GPIO(SPI_CS_L), A14, DIO_OUTPUT) 330 331PINMUX(GPIO(DIOB4), B4, DIO_INPUT) 332 333 334#undef PINMUX 335