xref: /aosp_15_r20/external/ethtool/smsc911x.c (revision 1b481fc3bb1b45d4cf28d1ec12969dc1055f555d)
1*1b481fc3SMaciej Żenczykowski #include <stdio.h>
2*1b481fc3SMaciej Żenczykowski #include <string.h>
3*1b481fc3SMaciej Żenczykowski #include "internal.h"
4*1b481fc3SMaciej Żenczykowski 
smsc911x_dump_regs(struct ethtool_drvinfo * info __maybe_unused,struct ethtool_regs * regs)5*1b481fc3SMaciej Żenczykowski int smsc911x_dump_regs(struct ethtool_drvinfo *info __maybe_unused,
6*1b481fc3SMaciej Żenczykowski 		       struct ethtool_regs *regs)
7*1b481fc3SMaciej Żenczykowski {
8*1b481fc3SMaciej Żenczykowski 	unsigned int *smsc_reg = (unsigned int *)regs->data;
9*1b481fc3SMaciej Żenczykowski 
10*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "LAN911x Registers\n");
11*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x50, ID_REV       = 0x%08X\n",*smsc_reg++);
12*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x54, INT_CFG      = 0x%08X\n",*smsc_reg++);
13*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x58, INT_STS      = 0x%08X\n",*smsc_reg++);
14*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x5C, INT_EN       = 0x%08X\n",*smsc_reg++);
15*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x60, RESERVED     = 0x%08X\n",*smsc_reg++);
16*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x64, BYTE_TEST    = 0x%08X\n",*smsc_reg++);
17*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x68, FIFO_INT     = 0x%08X\n",*smsc_reg++);
18*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x6C, RX_CFG       = 0x%08X\n",*smsc_reg++);
19*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x70, TX_CFG       = 0x%08X\n",*smsc_reg++);
20*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x74, HW_CFG       = 0x%08X\n",*smsc_reg++);
21*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x78, RX_DP_CTRL   = 0x%08X\n",*smsc_reg++);
22*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x7C, RX_FIFO_INF  = 0x%08X\n",*smsc_reg++);
23*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x80, TX_FIFO_INF  = 0x%08X\n",*smsc_reg++);
24*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x84, PMT_CTRL     = 0x%08X\n",*smsc_reg++);
25*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x88, GPIO_CFG     = 0x%08X\n",*smsc_reg++);
26*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x8C, GPT_CFG      = 0x%08X\n",*smsc_reg++);
27*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x90, GPT_CNT      = 0x%08X\n",*smsc_reg++);
28*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x94, FPGA_REV     = 0x%08X\n",*smsc_reg++);
29*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x98, ENDIAN       = 0x%08X\n",*smsc_reg++);
30*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0x9C, FREE_RUN     = 0x%08X\n",*smsc_reg++);
31*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0xA0, RX_DROP      = 0x%08X\n",*smsc_reg++);
32*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0xA4, MAC_CSR_CMD  = 0x%08X\n",*smsc_reg++);
33*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0xA8, MAC_CSR_DATA = 0x%08X\n",*smsc_reg++);
34*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0xAC, AFC_CFG      = 0x%08X\n",*smsc_reg++);
35*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0xB0, E2P_CMD      = 0x%08X\n",*smsc_reg++);
36*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "offset 0xB4, E2P_DATA     = 0x%08X\n",*smsc_reg++);
37*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "\n");
38*1b481fc3SMaciej Żenczykowski 
39*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "MAC Registers\n");
40*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 1, MAC_CR   = 0x%08X\n",*smsc_reg++);
41*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 2, ADDRH    = 0x%08X\n",*smsc_reg++);
42*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 3, ADDRL    = 0x%08X\n",*smsc_reg++);
43*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 4, HASHH    = 0x%08X\n",*smsc_reg++);
44*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 5, HASHL    = 0x%08X\n",*smsc_reg++);
45*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 6, MII_ACC  = 0x%08X\n",*smsc_reg++);
46*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 7, MII_DATA = 0x%08X\n",*smsc_reg++);
47*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 8, FLOW     = 0x%08X\n",*smsc_reg++);
48*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 9, VLAN1    = 0x%08X\n",*smsc_reg++);
49*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index A, VLAN2    = 0x%08X\n",*smsc_reg++);
50*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index B, WUFF     = 0x%08X\n",*smsc_reg++);
51*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index C, WUCSR    = 0x%08X\n",*smsc_reg++);
52*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "\n");
53*1b481fc3SMaciej Żenczykowski 
54*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "PHY Registers\n");
55*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 0, Basic Control Reg = 0x%04X\n",*smsc_reg++);
56*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 1, Basic Status Reg  = 0x%04X\n",*smsc_reg++);
57*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 2, PHY identifier 1  = 0x%04X\n",*smsc_reg++);
58*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 3, PHY identifier 2  = 0x%04X\n",*smsc_reg++);
59*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 4, Auto Negotiation Advertisement Reg = 0x%04X\n",*smsc_reg++);
60*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 5, Auto Negotiation Link Partner Ability Reg = 0x%04X\n",*smsc_reg++);
61*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 6, Auto Negotiation Expansion Register = 0x%04X\n",*smsc_reg++);
62*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 7, Reserved = 0x%04X\n",*smsc_reg++);
63*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 8, Reserved = 0x%04X\n",*smsc_reg++);
64*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 9, Reserved = 0x%04X\n",*smsc_reg++);
65*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 10, Reserved = 0x%04X\n",*smsc_reg++);
66*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 11, Reserved = 0x%04X\n",*smsc_reg++);
67*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 12, Reserved = 0x%04X\n",*smsc_reg++);
68*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 13, Reserved = 0x%04X\n",*smsc_reg++);
69*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 14, Reserved = 0x%04X\n",*smsc_reg++);
70*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 15, Reserved = 0x%04X\n",*smsc_reg++);
71*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 16, Silicon Revision Reg = 0x%04X\n",*smsc_reg++);
72*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 17, Mode Control/Status Reg = 0x%04X\n",*smsc_reg++);
73*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 18, Special Modes = 0x%04X\n",*smsc_reg++);
74*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 19, Reserved = 0x%04X\n",*smsc_reg++);
75*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 20, TSTCNTL = 0x%04X\n",*smsc_reg++);
76*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 21, TSTREAD1 = 0x%04X\n",*smsc_reg++);
77*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 22, TSTREAD2 = 0x%04X\n",*smsc_reg++);
78*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 23, TSTWRITE = 0x%04X\n",*smsc_reg++);
79*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 24, Reserved = 0x%04X\n",*smsc_reg++);
80*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 25, Reserved = 0x%04X\n",*smsc_reg++);
81*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 26, Reserved = 0x%04X\n",*smsc_reg++);
82*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 27, Control/Status Indication = 0x%04X\n",*smsc_reg++);
83*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 28, Special internal testability = 0x%04X\n",*smsc_reg++);
84*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 29, Interrupt Source Register = 0x%04X\n",*smsc_reg++);
85*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 30, Interrupt Mask Register = 0x%04X\n",*smsc_reg++);
86*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "index 31, PHY Special Control/Status Register = 0x%04X\n",*smsc_reg++);
87*1b481fc3SMaciej Żenczykowski 	fprintf(stdout, "\n");
88*1b481fc3SMaciej Żenczykowski 
89*1b481fc3SMaciej Żenczykowski 	return 0;
90*1b481fc3SMaciej Żenczykowski }
91*1b481fc3SMaciej Żenczykowski 
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