1 /* Copyright (c) 2020 Intel Corporation */
2 #include <stdio.h>
3 #include "internal.h"
4
5 #define RAH_RAH 0x0000FFFF
6 #define RAH_ASEL 0x00010000
7 #define RAH_QSEL 0x000C0000
8 #define RAH_QSEL_EN 0x10000000
9 #define RAH_AV 0x80000000
10 #define RCTL_RXEN 0x00000002
11 #define RCTL_SBP 0x00000004
12 #define RCTL_UPE 0x00000008
13 #define RCTL_MPE 0x00000010
14 #define RCTL_LPE 0x00000020
15 #define RCTL_LBM 0x000000C0
16 #define RCTL_LBM_PHY 0x00000000
17 #define RCTL_LBM_MAC 0x00000040
18 #define RCTL_HSEL 0x00000300
19 #define RCTL_HSEL_MULTICAST 0x00000000
20 #define RCTL_HSEL_UNICAST 0x00000100
21 #define RCTL_HSEL_BOTH 0x00000200
22 #define RCTL_MO 0x00003000
23 #define RCTL_MO_47_36 0x00000000
24 #define RCTL_MO_43_32 0x00001000
25 #define RCTL_MO_39_28 0x00002000
26 #define RCTL_BAM 0x00008000
27 #define RCTL_BSIZE 0x00030000
28 #define RCTL_BSIZE_2048 0x00000000
29 #define RCTL_BSIZE_1024 0x00010000
30 #define RCTL_BSIZE_512 0x00020000
31 #define RCTL_VFE 0x00040000
32 #define RCTL_CFIEN 0x00080000
33 #define RCTL_CFI 0x00100000
34 #define RCTL_PSP 0x00200000
35 #define RCTL_DPF 0x00400000
36 #define RCTL_PMCF 0x00800000
37 #define RCTL_SECRC 0x04000000
38 #define VLANPQF_VP0QSEL 0x00000003
39 #define VLANPQF_VP0PBSEL 0x00000004
40 #define VLANPQF_VLANP0V 0x00000008
41 #define VLANPQF_VP1QSEL 0x00000030
42 #define VLANPQF_VP1PBSEL 0x00000040
43 #define VLANPQF_VLANP1V 0x00000080
44 #define VLANPQF_VP2QSEL 0x00000300
45 #define VLANPQF_VP2PBSEL 0x00000400
46 #define VLANPQF_VLANP2V 0x00000800
47 #define VLANPQF_VP3QSEL 0x00003000
48 #define VLANPQF_VP3PBSEL 0x00004000
49 #define VLANPQF_VLANP3V 0x00008000
50 #define VLANPQF_VP4QSEL 0x00030000
51 #define VLANPQF_VP4PBSEL 0x00040000
52 #define VLANPQF_VLANP4V 0x00080000
53 #define VLANPQF_VP5QSEL 0x00300000
54 #define VLANPQF_VP5PBSEL 0x00400000
55 #define VLANPQF_VLANP5V 0x00800000
56 #define VLANPQF_VP6QSEL 0x03000000
57 #define VLANPQF_VP6PBSEL 0x04000000
58 #define VLANPQF_VLANP6V 0x08000000
59 #define VLANPQF_VP7QSEL 0x30000000
60 #define VLANPQF_VP7PBSEL 0x40000000
61 #define VLANPQF_VLANP7V 0x80000000
62 #define ETQF_ETYPE 0x0000FFFF
63 #define ETQF_QUEUE 0x00070000
64 #define ETQF_ETYPE_LEN 0x01F00000
65 #define ETQF_ETYPE_LEN_EN 0x02000000
66 #define ETQF_FILTER_EN 0x04000000
67 #define ETQF_IMMEDIATE_INTR 0x20000000
68 #define ETQF_1588_TIMESTAMP 0x40000000
69 #define ETQF_QUEUE_EN 0x80000000
70
71 #define RAH_QSEL_SHIFT 18
72 #define VLANPQF_VP1QSEL_SHIFT 4
73 #define VLANPQF_VP2QSEL_SHIFT 8
74 #define VLANPQF_VP3QSEL_SHIFT 12
75 #define VLANPQF_VP4QSEL_SHIFT 16
76 #define VLANPQF_VP5QSEL_SHIFT 20
77 #define VLANPQF_VP6QSEL_SHIFT 24
78 #define VLANPQF_VP7QSEL_SHIFT 28
79 #define ETQF_QUEUE_SHIFT 16
80 #define ETQF_ETYPE_LEN_SHIFT 20
81
bit_to_boolean(u32 val)82 static const char *bit_to_boolean(u32 val)
83 {
84 return val ? "yes" : "no";
85 }
86
bit_to_enable(u32 val)87 static const char *bit_to_enable(u32 val)
88 {
89 return val ? "enabled" : "disabled";
90 }
91
bit_to_prio(u32 val)92 static const char *bit_to_prio(u32 val)
93 {
94 return val ? "low" : "high";
95 }
96
igc_dump_regs(struct ethtool_drvinfo * info __maybe_unused,struct ethtool_regs * regs)97 int igc_dump_regs(struct ethtool_drvinfo *info __maybe_unused,
98 struct ethtool_regs *regs)
99 {
100 u32 reg;
101 int offset, i;
102 u32 *regs_buff = (u32 *)regs->data;
103 u8 version = (u8)(regs->version >> 24);
104
105 if (version != 2)
106 return -1;
107
108 for (offset = 0; offset < 24; offset++) {
109 reg = regs_buff[offset];
110 printf("%04d: 0x%08X\n", offset, reg);
111 }
112
113 offset = 24;
114
115 reg = regs_buff[offset];
116 printf("%04d: RCTL (Receive Control Register) \n"
117 " Receiver: %s\n"
118 " Stop Bad Packets: %s\n"
119 " Unicast Promiscuous: %s\n"
120 " Multicast Promiscuous: %s\n"
121 " Long Packet Reception: %s\n"
122 " Loopback Model: %s\n"
123 " Hash Select for MTA: %s\n"
124 " Multicast/Unicast Table Offset: %s\n"
125 " Broadcast Accept Mode: %s\n"
126 " Receive Buffer Size: %s\n"
127 " VLAN Filter: %s\n"
128 " Canonical Form Indicator: %s\n"
129 " Canonical Form Indicator Bit: %s\n"
130 " Pad Small Receive Packets: %s\n"
131 " Discard Pause Frames: %s\n"
132 " Pass MAC Control Frames: %s\n"
133 " Strip Ethernet CRC: %s\n",
134 offset,
135 bit_to_enable(reg & RCTL_RXEN),
136 bit_to_enable(reg & RCTL_SBP),
137 bit_to_enable(reg & RCTL_UPE),
138 bit_to_enable(reg & RCTL_MPE),
139 bit_to_enable(reg & RCTL_LPE),
140 (reg & RCTL_LBM) == RCTL_LBM_PHY ? "PHY" :
141 (reg & RCTL_LBM) == RCTL_LBM_MAC ? "MAC" :
142 "undefined",
143 (reg & RCTL_HSEL) == RCTL_HSEL_MULTICAST ? "multicast only" :
144 (reg & RCTL_HSEL) == RCTL_HSEL_UNICAST ? "unicast only" :
145 (reg & RCTL_HSEL) == RCTL_HSEL_BOTH ? "multicast and unicast" :
146 "reserved",
147 (reg & RCTL_MO) == RCTL_MO_47_36 ? "bits [47:36]" :
148 (reg & RCTL_MO) == RCTL_MO_43_32 ? "bits [43:32]" :
149 (reg & RCTL_MO) == RCTL_MO_39_28 ? "bits [39:28]" :
150 "bits [35:24]",
151 bit_to_enable(reg & RCTL_BAM),
152 (reg & RCTL_BSIZE) == RCTL_BSIZE_2048 ? "2048 bytes" :
153 (reg & RCTL_BSIZE) == RCTL_BSIZE_1024 ? "1024 bytes" :
154 (reg & RCTL_BSIZE) == RCTL_BSIZE_512 ? "512 bytes" :
155 "256 bytes",
156 bit_to_enable(reg & RCTL_VFE),
157 bit_to_enable(reg & RCTL_CFIEN),
158 reg & RCTL_CFI ? "discarded" : "accepted",
159 bit_to_enable(reg & RCTL_PSP),
160 bit_to_enable(reg & RCTL_DPF),
161 bit_to_enable(reg & RCTL_PMCF),
162 bit_to_enable(reg & RCTL_SECRC));
163
164 for (offset = 25; offset < 172; offset++) {
165 reg = regs_buff[offset];
166 printf("%04d: 0x%08X\n", offset, reg);
167 }
168
169 offset = 172;
170
171 for (i = 0; i < 16; i++) {
172 reg = regs_buff[offset + i];
173 printf("%04d: RAL (Receive Address Low %02d) \n"
174 " Receive Address Low: %08X\n",
175 offset + i, i,
176 reg);
177 }
178
179 offset = 188;
180
181 for (i = 0; i < 16; i++) {
182 reg = regs_buff[offset + i];
183 printf("%04d: RAH (Receive Address High %02d) \n"
184 " Receive Address High: %04X\n"
185 " Address Select: %s\n"
186 " Queue Select: %d\n"
187 " Queue Select Enable: %s\n"
188 " Address Valid: %s\n",
189 offset + i, i,
190 reg & RAH_RAH,
191 reg & RAH_ASEL ? "source" : "destination",
192 (reg & RAH_QSEL) >> RAH_QSEL_SHIFT,
193 bit_to_boolean(reg & RAH_QSEL_EN),
194 bit_to_boolean(reg & RAH_AV));
195 }
196
197 offset = 204;
198
199 reg = regs_buff[offset];
200 printf("%04d: VLANPQF (VLAN Priority Queue Filter) \n"
201 " Priority 0 \n"
202 " Queue: %d\n"
203 " Packet Buffer: %s\n"
204 " Valid: %s\n"
205 " Priority 1 \n"
206 " Queue: %d\n"
207 " Packet Buffer: %s\n"
208 " Valid: %s\n"
209 " Priority 2 \n"
210 " Queue: %d\n"
211 " Packet Buffer: %s\n"
212 " Valid: %s\n"
213 " Priority 3 \n"
214 " Queue: %d\n"
215 " Packet Buffer: %s\n"
216 " Valid: %s\n"
217 " Priority 4 \n"
218 " Queue: %d\n"
219 " Packet Buffer: %s\n"
220 " Valid: %s\n"
221 " Priority 5 \n"
222 " Queue: %d\n"
223 " Packet Buffer: %s\n"
224 " Valid: %s\n"
225 " Priority 6 \n"
226 " Queue: %d\n"
227 " Packet Buffer: %s\n"
228 " Valid: %s\n"
229 " Priority 7 \n"
230 " Queue: %d\n"
231 " Packet Buffer: %s\n"
232 " Valid: %s\n",
233 offset,
234 reg & VLANPQF_VP0QSEL,
235 bit_to_prio(reg & VLANPQF_VP0PBSEL),
236 bit_to_boolean(reg & VLANPQF_VLANP0V),
237 (reg & VLANPQF_VP1QSEL) >> VLANPQF_VP1QSEL_SHIFT,
238 bit_to_prio(reg & VLANPQF_VP1PBSEL),
239 bit_to_boolean(reg & VLANPQF_VLANP1V),
240 (reg & VLANPQF_VP2QSEL) >> VLANPQF_VP2QSEL_SHIFT,
241 bit_to_prio(reg & VLANPQF_VP2PBSEL),
242 bit_to_boolean(reg & VLANPQF_VLANP2V),
243 (reg & VLANPQF_VP3QSEL) >> VLANPQF_VP3QSEL_SHIFT,
244 bit_to_prio(reg & VLANPQF_VP3PBSEL),
245 bit_to_boolean(reg & VLANPQF_VLANP3V),
246 (reg & VLANPQF_VP4QSEL) >> VLANPQF_VP4QSEL_SHIFT,
247 bit_to_prio(reg & VLANPQF_VP4PBSEL),
248 bit_to_boolean(reg & VLANPQF_VLANP4V),
249 (reg & VLANPQF_VP5QSEL) >> VLANPQF_VP5QSEL_SHIFT,
250 bit_to_prio(reg & VLANPQF_VP5PBSEL),
251 bit_to_boolean(reg & VLANPQF_VLANP5V),
252 (reg & VLANPQF_VP6QSEL) >> VLANPQF_VP6QSEL_SHIFT,
253 bit_to_prio(reg & VLANPQF_VP6PBSEL),
254 bit_to_boolean(reg & VLANPQF_VLANP6V),
255 (reg & VLANPQF_VP7QSEL) >> VLANPQF_VP7QSEL_SHIFT,
256 bit_to_prio(reg & VLANPQF_VP7PBSEL),
257 bit_to_boolean(reg & VLANPQF_VLANP7V));
258
259 offset = 205;
260
261 for (i = 0; i < 8; i++) {
262 reg = regs_buff[offset + i];
263 printf("%04d: ETQF (EType Queue Filter %d) \n"
264 " EType: %04X\n"
265 " EType Length: %d\n"
266 " EType Length Enable: %s\n"
267 " Queue: %d\n"
268 " Queue Enable: %s\n"
269 " Immediate Interrupt: %s\n"
270 " 1588 Time Stamp: %s\n"
271 " Filter Enable: %s\n",
272 offset + i, i,
273 reg & ETQF_ETYPE,
274 (reg & ETQF_ETYPE_LEN) >> ETQF_ETYPE_LEN_SHIFT,
275 bit_to_boolean(reg & ETQF_ETYPE_LEN_EN),
276 (reg & ETQF_QUEUE) >> ETQF_QUEUE_SHIFT,
277 bit_to_boolean(reg & ETQF_QUEUE_EN),
278 bit_to_enable(reg & ETQF_IMMEDIATE_INTR),
279 bit_to_enable(reg & ETQF_1588_TIMESTAMP),
280 bit_to_boolean(reg & ETQF_FILTER_EN));
281 }
282
283 return 0;
284 }
285