1*1b481fc3SMaciej Żenczykowski #include <stdio.h>
2*1b481fc3SMaciej Żenczykowski #include <string.h>
3*1b481fc3SMaciej Żenczykowski #include "internal.h"
4*1b481fc3SMaciej Żenczykowski
et131x_dump_regs(struct ethtool_drvinfo * info __maybe_unused,struct ethtool_regs * regs)5*1b481fc3SMaciej Żenczykowski int et131x_dump_regs(struct ethtool_drvinfo *info __maybe_unused,
6*1b481fc3SMaciej Żenczykowski struct ethtool_regs *regs)
7*1b481fc3SMaciej Żenczykowski {
8*1b481fc3SMaciej Żenczykowski u8 version = (u8)(regs->version >> 24);
9*1b481fc3SMaciej Żenczykowski u32 *reg = (u32 *)regs->data;
10*1b481fc3SMaciej Żenczykowski
11*1b481fc3SMaciej Żenczykowski if (version != 1)
12*1b481fc3SMaciej Żenczykowski return -1;
13*1b481fc3SMaciej Żenczykowski
14*1b481fc3SMaciej Żenczykowski fprintf(stdout, "PHY Registers\n");
15*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x0, Basic Control Reg = 0x%04X\n", *reg++);
16*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1, Basic Status Reg = 0x%04X\n", *reg++);
17*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x2, PHY identifier 1 = 0x%04X\n", *reg++);
18*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x3, PHY identifier 2 = 0x%04X\n", *reg++);
19*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x4, Auto Neg Advertisement = 0x%04X\n", *reg++);
20*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x5, Auto Neg L Partner Ability = 0x%04X\n", *reg++);
21*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x6, Auto Neg Expansion = 0x%04X\n", *reg++);
22*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x7, Reserved = 0x%04X\n", *reg++);
23*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x8, Reserved = 0x%04X\n", *reg++);
24*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x9, 1000T Control = 0x%04X\n", *reg++);
25*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xA, 1000T Status = 0x%04X\n", *reg++);
26*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xB, Reserved = 0x%04X\n", *reg++);
27*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xC, Reserved = 0x%04X\n", *reg++);
28*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xD, MMD Access Control = 0x%04X\n", *reg++);
29*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xE, MMD access Data = 0x%04X\n", *reg++);
30*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xF, Extended Status = 0x%04X\n", *reg++);
31*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x10, Phy Index = 0x%04X\n", *reg++);
32*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x11, Phy Data = 0x%04X\n", *reg++);
33*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x12, MPhy Control = 0x%04X\n", *reg++);
34*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x13, Phy Loopback Control1 = 0x%04X\n", *reg++);
35*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x14, Phy Loopback Control2 = 0x%04X\n", *reg++);
36*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x15, Register Management = 0x%04X\n", *reg++);
37*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x16, Phy Config = 0x%04X\n", *reg++);
38*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x17, Phy Phy Control = 0x%04X\n", *reg++);
39*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x18, Phy Interrupt Mask = 0x%04X\n", *reg++);
40*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x19, Phy Interrupt Status = 0x%04X\n", *reg++);
41*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1A, Phy Phy Status = 0x%04X\n", *reg++);
42*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1B, Phy LED1 = 0x%04X\n", *reg++);
43*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1C, Phy LED2 = 0x%04X\n", *reg++);
44*1b481fc3SMaciej Żenczykowski fprintf(stdout, "\n");
45*1b481fc3SMaciej Żenczykowski
46*1b481fc3SMaciej Żenczykowski fprintf(stdout, "JAGCore Global Registers\n");
47*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x0, TXQ Start Address = 0x%04X\n", *reg++);
48*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1, TXQ End Address = 0x%04X\n", *reg++);
49*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x2, RXQ Start Address = 0x%04X\n", *reg++);
50*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x3, RXQ End Address = 0x%04X\n", *reg++);
51*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x4, Power Management Status = 0x%04X\n", *reg++);
52*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x5, Interrupt Status = 0x%04X\n", *reg++);
53*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x6, Interrupt Mask = 0x%04X\n", *reg++);
54*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x7, Int Alias Clear Mask = 0x%04X\n", *reg++);
55*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x8, Int Status Alias = 0x%04X\n", *reg++);
56*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x9, Software Reset = 0x%04X\n", *reg++);
57*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xA, SLV Timer = 0x%04X\n", *reg++);
58*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xB, MSI Config = 0x%04X\n", *reg++);
59*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xC, Loopback = 0x%04X\n", *reg++);
60*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xD, Watchdog Timer = 0x%04X\n", *reg++);
61*1b481fc3SMaciej Żenczykowski fprintf(stdout, "\n");
62*1b481fc3SMaciej Żenczykowski
63*1b481fc3SMaciej Żenczykowski fprintf(stdout, "TXDMA Registers\n");
64*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x0, Control Status = 0x%04X\n", *reg++);
65*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1, Packet Ring Base Addr (Hi) = 0x%04X\n", *reg++);
66*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x2, Packet Ring Base Addr (Lo) = 0x%04X\n", *reg++);
67*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x3, Packet Ring Num Descrs = 0x%04X\n", *reg++);
68*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x4, TX Queue Write Address = 0x%04X\n", *reg++);
69*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x5, TX Queue Write Address Ext = 0x%04X\n", *reg++);
70*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x6, TX Queue Read Address = 0x%04X\n", *reg++);
71*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x7, Status Writeback Addr (Hi) = 0x%04X\n", *reg++);
72*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x8, Status Writeback Addr (Lo) = 0x%04X\n", *reg++);
73*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x9, Service Request = 0x%04X\n", *reg++);
74*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xA, Service Complete = 0x%04X\n", *reg++);
75*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xB, Cache Read Index = 0x%04X\n", *reg++);
76*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xC, Cache Write Index = 0x%04X\n", *reg++);
77*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xD, TXDMA Error = 0x%04X\n", *reg++);
78*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xE, Descriptor Abort Count = 0x%04X\n", *reg++);
79*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xF, Payload Abort Count = 0x%04X\n", *reg++);
80*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x10, Writeback Abort Count = 0x%04X\n", *reg++);
81*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x11, Descriptor Timeout Count = 0x%04X\n", *reg++);
82*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x12, Payload Timeout Count = 0x%04X\n", *reg++);
83*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x13, Writeback Timeout Count = 0x%04X\n", *reg++);
84*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x14, Descriptor Error Count = 0x%04X\n", *reg++);
85*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x15, Payload Error Count = 0x%04X\n", *reg++);
86*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x16, Writeback Error Count = 0x%04X\n", *reg++);
87*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x17, Dropped TLP Count = 0x%04X\n", *reg++);
88*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x18, New service Complete = 0x%04X\n", *reg++);
89*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1A, Ethernet Packet Count = 0x%04X\n", *reg++);
90*1b481fc3SMaciej Żenczykowski fprintf(stdout, "\n");
91*1b481fc3SMaciej Żenczykowski
92*1b481fc3SMaciej Żenczykowski fprintf(stdout, "RXDMA Registers\n");
93*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x0, Control Status = 0x%04X\n", *reg++);
94*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1, Writeback Addr (Hi) = 0x%04X\n", *reg++);
95*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x2, Writeback Addr (Lo) = 0x%04X\n", *reg++);
96*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x3, Num Packets Done = 0x%04X\n", *reg++);
97*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x4, Max Packet Time = 0x%04X\n", *reg++);
98*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x5, RX Queue Read Addr = 0x%04X\n", *reg++);
99*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x6, RX Queue Read Address Ext = 0x%04X\n", *reg++);
100*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x7, RX Queue Write Addr = 0x%04X\n", *reg++);
101*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x8, Packet Ring Base Addr (Hi) = 0x%04X\n", *reg++);
102*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x9, Packet Ring Base Addr (Lo) = 0x%04X\n", *reg++);
103*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xA, Packet Ring Num Descrs = 0x%04X\n", *reg++);
104*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xE, Packet Ring Avail Offset = 0x%04X\n", *reg++);
105*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0xF, Packet Ring Full Offset = 0x%04X\n", *reg++);
106*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x10, Packet Ring Access Index = 0x%04X\n", *reg++);
107*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x11, Packet Ring Min Descrip = 0x%04X\n", *reg++);
108*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x12, FBR0 Address (Lo) = 0x%04X\n", *reg++);
109*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x13, FBR0 Address (Hi) = 0x%04X\n", *reg++);
110*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x14, FBR0 Num Descriptors = 0x%04X\n", *reg++);
111*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x15, FBR0 Available Offset = 0x%04X\n", *reg++);
112*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x16, FBR0 Full Offset = 0x%04X\n", *reg++);
113*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x17, FBR0 Read Index = 0x%04X\n", *reg++);
114*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x18, FBR0 Minimum Descriptors = 0x%04X\n", *reg++);
115*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x19, FBR1 Address (Lo) = 0x%04X\n", *reg++);
116*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1A, FBR1 Address (Hi) = 0x%04X\n", *reg++);
117*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1B, FBR1 Num Descriptors = 0x%04X\n", *reg++);
118*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1C, FBR1 Available Offset = 0x%04X\n", *reg++);
119*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1D, FBR1 Full Offset = 0x%04X\n", *reg++);
120*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1E, FBR1 Read Index = 0x%04X\n", *reg++);
121*1b481fc3SMaciej Żenczykowski fprintf(stdout, "0x1F, FBR1 Minimum Descriptors = 0x%04X\n", *reg++);
122*1b481fc3SMaciej Żenczykowski fprintf(stdout, "\n");
123*1b481fc3SMaciej Żenczykowski return 0;
124*1b481fc3SMaciej Żenczykowski }
125