1*2b54f0dbSXin Li #pragma once 2*2b54f0dbSXin Li 3*2b54f0dbSXin Li /* List of known and supported Windows on Arm SoCs/chips. */ 4*2b54f0dbSXin Li enum woa_chip_name { 5*2b54f0dbSXin Li woa_chip_name_microsoft_sq_1 = 0, 6*2b54f0dbSXin Li woa_chip_name_microsoft_sq_2 = 1, 7*2b54f0dbSXin Li woa_chip_name_unknown = 2, 8*2b54f0dbSXin Li woa_chip_name_last = woa_chip_name_unknown 9*2b54f0dbSXin Li }; 10*2b54f0dbSXin Li 11*2b54f0dbSXin Li /* Topology information hard-coded by SoC/chip name */ 12*2b54f0dbSXin Li struct core_info_by_chip_name { 13*2b54f0dbSXin Li enum cpuinfo_uarch uarch; 14*2b54f0dbSXin Li uint64_t frequency; /* Hz */ 15*2b54f0dbSXin Li }; 16*2b54f0dbSXin Li 17*2b54f0dbSXin Li /* SoC/chip info that's currently not readable by logical system information, 18*2b54f0dbSXin Li * but can be read from registry. 19*2b54f0dbSXin Li */ 20*2b54f0dbSXin Li struct woa_chip_info { 21*2b54f0dbSXin Li char* chip_name_string; 22*2b54f0dbSXin Li enum woa_chip_name chip_name; 23*2b54f0dbSXin Li struct core_info_by_chip_name uarchs[woa_chip_name_last]; 24*2b54f0dbSXin Li }; 25*2b54f0dbSXin Li 26*2b54f0dbSXin Li bool get_core_uarch_for_efficiency( 27*2b54f0dbSXin Li enum woa_chip_name chip, BYTE EfficiencyClass, 28*2b54f0dbSXin Li enum cpuinfo_uarch* uarch, uint64_t* frequency); 29*2b54f0dbSXin Li 30*2b54f0dbSXin Li bool cpu_info_init_by_logical_sys_info( 31*2b54f0dbSXin Li const struct woa_chip_info *chip_info, 32*2b54f0dbSXin Li enum cpuinfo_vendor vendor); 33