1*2b54f0dbSXin Li #include <stdint.h> 2*2b54f0dbSXin Li 3*2b54f0dbSXin Li 4*2b54f0dbSXin Li #if CPUINFO_MOCK 5*2b54f0dbSXin Li extern uint32_t cpuinfo_arm_fpsid; 6*2b54f0dbSXin Li extern uint32_t cpuinfo_arm_mvfr0; 7*2b54f0dbSXin Li extern uint32_t cpuinfo_arm_wcid; 8*2b54f0dbSXin Li read_fpsid(void)9*2b54f0dbSXin Li static inline uint32_t read_fpsid(void) { 10*2b54f0dbSXin Li return cpuinfo_arm_fpsid; 11*2b54f0dbSXin Li } 12*2b54f0dbSXin Li read_mvfr0(void)13*2b54f0dbSXin Li static inline uint32_t read_mvfr0(void) { 14*2b54f0dbSXin Li return cpuinfo_arm_mvfr0; 15*2b54f0dbSXin Li } 16*2b54f0dbSXin Li read_wcid(void)17*2b54f0dbSXin Li static inline uint32_t read_wcid(void) { 18*2b54f0dbSXin Li return cpuinfo_arm_wcid; 19*2b54f0dbSXin Li } 20*2b54f0dbSXin Li #else 21*2b54f0dbSXin Li #if !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 7)) 22*2b54f0dbSXin Li /* 23*2b54f0dbSXin Li * CoProcessor 10 is inaccessible from user mode since ARMv7, 24*2b54f0dbSXin Li * and clang refuses to compile inline assembly when targeting ARMv7+ 25*2b54f0dbSXin Li */ read_fpsid(void)26*2b54f0dbSXin Li static inline uint32_t read_fpsid(void) { 27*2b54f0dbSXin Li uint32_t fpsid; 28*2b54f0dbSXin Li __asm__ __volatile__("MRC p10, 0x7, %[fpsid], cr0, cr0, 0" : [fpsid] "=r" (fpsid)); 29*2b54f0dbSXin Li return fpsid; 30*2b54f0dbSXin Li } 31*2b54f0dbSXin Li read_mvfr0(void)32*2b54f0dbSXin Li static inline uint32_t read_mvfr0(void) { 33*2b54f0dbSXin Li uint32_t mvfr0; 34*2b54f0dbSXin Li __asm__ __volatile__("MRC p10, 0x7, %[mvfr0], cr7, cr0, 0" : [mvfr0] "=r" (mvfr0)); 35*2b54f0dbSXin Li return mvfr0; 36*2b54f0dbSXin Li } 37*2b54f0dbSXin Li #endif 38*2b54f0dbSXin Li read_wcid(void)39*2b54f0dbSXin Li static inline uint32_t read_wcid(void) { 40*2b54f0dbSXin Li uint32_t wcid; 41*2b54f0dbSXin Li __asm__ __volatile__("MRC p1, 0, %[wcid], c0, c0" : [wcid] "=r" (wcid)); 42*2b54f0dbSXin Li return wcid; 43*2b54f0dbSXin Li } 44*2b54f0dbSXin Li #endif 45