1*2b54f0dbSXin Li #include <stdint.h>
2*2b54f0dbSXin Li
3*2b54f0dbSXin Li #include <arm/linux/api.h>
4*2b54f0dbSXin Li #include <cpuinfo/log.h>
5*2b54f0dbSXin Li
6*2b54f0dbSXin Li
cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo(uint32_t features,uint32_t features2,uint32_t midr,const struct cpuinfo_arm_chipset chipset[restrict static1],struct cpuinfo_arm_isa isa[restrict static1])7*2b54f0dbSXin Li void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo(
8*2b54f0dbSXin Li uint32_t features,
9*2b54f0dbSXin Li uint32_t features2,
10*2b54f0dbSXin Li uint32_t midr,
11*2b54f0dbSXin Li const struct cpuinfo_arm_chipset chipset[restrict static 1],
12*2b54f0dbSXin Li struct cpuinfo_arm_isa isa[restrict static 1])
13*2b54f0dbSXin Li {
14*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_AES) {
15*2b54f0dbSXin Li isa->aes = true;
16*2b54f0dbSXin Li }
17*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_PMULL) {
18*2b54f0dbSXin Li isa->pmull = true;
19*2b54f0dbSXin Li }
20*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_SHA1) {
21*2b54f0dbSXin Li isa->sha1 = true;
22*2b54f0dbSXin Li }
23*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_SHA2) {
24*2b54f0dbSXin Li isa->sha2 = true;
25*2b54f0dbSXin Li }
26*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_CRC32) {
27*2b54f0dbSXin Li isa->crc32 = true;
28*2b54f0dbSXin Li }
29*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_ATOMICS) {
30*2b54f0dbSXin Li isa->atomics = true;
31*2b54f0dbSXin Li }
32*2b54f0dbSXin Li
33*2b54f0dbSXin Li /*
34*2b54f0dbSXin Li * Some phones ship with an old kernel configuration that doesn't report NEON FP16 compute extension and SQRDMLAH/SQRDMLSH/UQRDMLAH/UQRDMLSH instructions.
35*2b54f0dbSXin Li * Use a MIDR-based heuristic to whitelist processors known to support it:
36*2b54f0dbSXin Li * - Processors with Cortex-A55 cores
37*2b54f0dbSXin Li * - Processors with Cortex-A65 cores
38*2b54f0dbSXin Li * - Processors with Cortex-A75 cores
39*2b54f0dbSXin Li * - Processors with Cortex-A76 cores
40*2b54f0dbSXin Li * - Processors with Cortex-A77 cores
41*2b54f0dbSXin Li * - Processors with Exynos M4 cores
42*2b54f0dbSXin Li * - Processors with Exynos M5 cores
43*2b54f0dbSXin Li * - Neoverse N1 cores
44*2b54f0dbSXin Li * - Neoverse V1 cores
45*2b54f0dbSXin Li * - Neoverse N2 cores
46*2b54f0dbSXin Li */
47*2b54f0dbSXin Li if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos && chipset->model == 9810) {
48*2b54f0dbSXin Li /* Exynos 9810 reports that it supports FP16 compute, but in fact only little cores do */
49*2b54f0dbSXin Li cpuinfo_log_warning("FP16 arithmetics and RDM disabled: only little cores in Exynos 9810 support these extensions");
50*2b54f0dbSXin Li } else {
51*2b54f0dbSXin Li const uint32_t fp16arith_mask = CPUINFO_ARM_LINUX_FEATURE_FPHP | CPUINFO_ARM_LINUX_FEATURE_ASIMDHP;
52*2b54f0dbSXin Li switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
53*2b54f0dbSXin Li case UINT32_C(0x4100D050): /* Cortex-A55 */
54*2b54f0dbSXin Li case UINT32_C(0x4100D060): /* Cortex-A65 */
55*2b54f0dbSXin Li case UINT32_C(0x4100D0B0): /* Cortex-A76 */
56*2b54f0dbSXin Li case UINT32_C(0x4100D0C0): /* Neoverse N1 */
57*2b54f0dbSXin Li case UINT32_C(0x4100D0D0): /* Cortex-A77 */
58*2b54f0dbSXin Li case UINT32_C(0x4100D0E0): /* Cortex-A76AE */
59*2b54f0dbSXin Li case UINT32_C(0x4100D400): /* Neoverse V1 */
60*2b54f0dbSXin Li case UINT32_C(0x4100D490): /* Neoverse N2 */
61*2b54f0dbSXin Li case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */
62*2b54f0dbSXin Li case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */
63*2b54f0dbSXin Li case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */
64*2b54f0dbSXin Li case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */
65*2b54f0dbSXin Li case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */
66*2b54f0dbSXin Li case UINT32_C(0x53000030): /* Exynos M4 */
67*2b54f0dbSXin Li case UINT32_C(0x53000040): /* Exynos M5 */
68*2b54f0dbSXin Li isa->fp16arith = true;
69*2b54f0dbSXin Li isa->rdm = true;
70*2b54f0dbSXin Li break;
71*2b54f0dbSXin Li default:
72*2b54f0dbSXin Li if ((features & fp16arith_mask) == fp16arith_mask) {
73*2b54f0dbSXin Li isa->fp16arith = true;
74*2b54f0dbSXin Li } else if (features & CPUINFO_ARM_LINUX_FEATURE_FPHP) {
75*2b54f0dbSXin Li cpuinfo_log_warning("FP16 arithmetics disabled: detected support only for scalar operations");
76*2b54f0dbSXin Li } else if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDHP) {
77*2b54f0dbSXin Li cpuinfo_log_warning("FP16 arithmetics disabled: detected support only for SIMD operations");
78*2b54f0dbSXin Li }
79*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM) {
80*2b54f0dbSXin Li isa->rdm = true;
81*2b54f0dbSXin Li }
82*2b54f0dbSXin Li break;
83*2b54f0dbSXin Li }
84*2b54f0dbSXin Li }
85*2b54f0dbSXin Li if (features2 & CPUINFO_ARM_LINUX_FEATURE2_I8MM) {
86*2b54f0dbSXin Li isa->i8mm = true;
87*2b54f0dbSXin Li }
88*2b54f0dbSXin Li
89*2b54f0dbSXin Li /*
90*2b54f0dbSXin Li * Many phones ship with an old kernel configuration that doesn't report UDOT/SDOT instructions.
91*2b54f0dbSXin Li * Use a MIDR-based heuristic to whitelist processors known to support it.
92*2b54f0dbSXin Li */
93*2b54f0dbSXin Li switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) {
94*2b54f0dbSXin Li case UINT32_C(0x4100D060): /* Cortex-A65 */
95*2b54f0dbSXin Li case UINT32_C(0x4100D0B0): /* Cortex-A76 */
96*2b54f0dbSXin Li case UINT32_C(0x4100D0C0): /* Neoverse N1 */
97*2b54f0dbSXin Li case UINT32_C(0x4100D0D0): /* Cortex-A77 */
98*2b54f0dbSXin Li case UINT32_C(0x4100D0E0): /* Cortex-A76AE */
99*2b54f0dbSXin Li case UINT32_C(0x4100D400): /* Neoverse V1 */
100*2b54f0dbSXin Li case UINT32_C(0x4100D490): /* Neoverse N2 */
101*2b54f0dbSXin Li case UINT32_C(0x4100D4A0): /* Neoverse E1 */
102*2b54f0dbSXin Li case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */
103*2b54f0dbSXin Li case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */
104*2b54f0dbSXin Li case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */
105*2b54f0dbSXin Li case UINT32_C(0x53000030): /* Exynos-M4 */
106*2b54f0dbSXin Li case UINT32_C(0x53000040): /* Exynos-M5 */
107*2b54f0dbSXin Li isa->dot = true;
108*2b54f0dbSXin Li break;
109*2b54f0dbSXin Li case UINT32_C(0x4100D050): /* Cortex A55: revision 1 or later only */
110*2b54f0dbSXin Li isa->dot = !!(midr_get_variant(midr) >= 1);
111*2b54f0dbSXin Li break;
112*2b54f0dbSXin Li case UINT32_C(0x4100D0A0): /* Cortex A75: revision 2 or later only */
113*2b54f0dbSXin Li isa->dot = !!(midr_get_variant(midr) >= 2);
114*2b54f0dbSXin Li break;
115*2b54f0dbSXin Li default:
116*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDDP) {
117*2b54f0dbSXin Li isa->dot = true;
118*2b54f0dbSXin Li }
119*2b54f0dbSXin Li break;
120*2b54f0dbSXin Li }
121*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_JSCVT) {
122*2b54f0dbSXin Li isa->jscvt = true;
123*2b54f0dbSXin Li }
124*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_JSCVT) {
125*2b54f0dbSXin Li isa->jscvt = true;
126*2b54f0dbSXin Li }
127*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_FCMA) {
128*2b54f0dbSXin Li isa->fcma = true;
129*2b54f0dbSXin Li }
130*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_SVE) {
131*2b54f0dbSXin Li isa->sve = true;
132*2b54f0dbSXin Li }
133*2b54f0dbSXin Li if (features2 & CPUINFO_ARM_LINUX_FEATURE2_SVE2) {
134*2b54f0dbSXin Li isa->sve2 = true;
135*2b54f0dbSXin Li }
136*2b54f0dbSXin Li // SVEBF16 is set iff SVE and BF16 are both supported, but the SVEBF16 feature flag
137*2b54f0dbSXin Li // was added in Linux kernel before the BF16 feature flag, so we check for either.
138*2b54f0dbSXin Li if (features2 & (CPUINFO_ARM_LINUX_FEATURE2_BF16 | CPUINFO_ARM_LINUX_FEATURE2_SVEBF16)) {
139*2b54f0dbSXin Li isa->bf16 = true;
140*2b54f0dbSXin Li }
141*2b54f0dbSXin Li if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDFHM) {
142*2b54f0dbSXin Li isa->fhm = true;
143*2b54f0dbSXin Li }
144*2b54f0dbSXin Li }
145*2b54f0dbSXin Li
146