1*2b54f0dbSXin Li #pragma once 2*2b54f0dbSXin Li 3*2b54f0dbSXin Li #include <stdbool.h> 4*2b54f0dbSXin Li #include <stdint.h> 5*2b54f0dbSXin Li 6*2b54f0dbSXin Li #include <cpuinfo.h> 7*2b54f0dbSXin Li #include <cpuinfo/common.h> 8*2b54f0dbSXin Li 9*2b54f0dbSXin Li enum cpuinfo_arm_chipset_vendor { 10*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_unknown = 0, 11*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_qualcomm, 12*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_mediatek, 13*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_samsung, 14*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_hisilicon, 15*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_actions, 16*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_allwinner, 17*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_amlogic, 18*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_broadcom, 19*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_lg, 20*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_leadcore, 21*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_marvell, 22*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_mstar, 23*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_novathor, 24*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_nvidia, 25*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_pinecone, 26*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_renesas, 27*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_rockchip, 28*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_spreadtrum, 29*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_telechips, 30*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_texas_instruments, 31*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_wondermedia, 32*2b54f0dbSXin Li cpuinfo_arm_chipset_vendor_max, 33*2b54f0dbSXin Li }; 34*2b54f0dbSXin Li 35*2b54f0dbSXin Li enum cpuinfo_arm_chipset_series { 36*2b54f0dbSXin Li cpuinfo_arm_chipset_series_unknown = 0, 37*2b54f0dbSXin Li cpuinfo_arm_chipset_series_qualcomm_qsd, 38*2b54f0dbSXin Li cpuinfo_arm_chipset_series_qualcomm_msm, 39*2b54f0dbSXin Li cpuinfo_arm_chipset_series_qualcomm_apq, 40*2b54f0dbSXin Li cpuinfo_arm_chipset_series_qualcomm_snapdragon, 41*2b54f0dbSXin Li cpuinfo_arm_chipset_series_mediatek_mt, 42*2b54f0dbSXin Li cpuinfo_arm_chipset_series_samsung_exynos, 43*2b54f0dbSXin Li cpuinfo_arm_chipset_series_hisilicon_k3v, 44*2b54f0dbSXin Li cpuinfo_arm_chipset_series_hisilicon_hi, 45*2b54f0dbSXin Li cpuinfo_arm_chipset_series_hisilicon_kirin, 46*2b54f0dbSXin Li cpuinfo_arm_chipset_series_actions_atm, 47*2b54f0dbSXin Li cpuinfo_arm_chipset_series_allwinner_a, 48*2b54f0dbSXin Li cpuinfo_arm_chipset_series_amlogic_aml, 49*2b54f0dbSXin Li cpuinfo_arm_chipset_series_amlogic_s, 50*2b54f0dbSXin Li cpuinfo_arm_chipset_series_broadcom_bcm, 51*2b54f0dbSXin Li cpuinfo_arm_chipset_series_lg_nuclun, 52*2b54f0dbSXin Li cpuinfo_arm_chipset_series_leadcore_lc, 53*2b54f0dbSXin Li cpuinfo_arm_chipset_series_marvell_pxa, 54*2b54f0dbSXin Li cpuinfo_arm_chipset_series_mstar_6a, 55*2b54f0dbSXin Li cpuinfo_arm_chipset_series_novathor_u, 56*2b54f0dbSXin Li cpuinfo_arm_chipset_series_nvidia_tegra_t, 57*2b54f0dbSXin Li cpuinfo_arm_chipset_series_nvidia_tegra_ap, 58*2b54f0dbSXin Li cpuinfo_arm_chipset_series_nvidia_tegra_sl, 59*2b54f0dbSXin Li cpuinfo_arm_chipset_series_pinecone_surge_s, 60*2b54f0dbSXin Li cpuinfo_arm_chipset_series_renesas_mp, 61*2b54f0dbSXin Li cpuinfo_arm_chipset_series_rockchip_rk, 62*2b54f0dbSXin Li cpuinfo_arm_chipset_series_spreadtrum_sc, 63*2b54f0dbSXin Li cpuinfo_arm_chipset_series_telechips_tcc, 64*2b54f0dbSXin Li cpuinfo_arm_chipset_series_texas_instruments_omap, 65*2b54f0dbSXin Li cpuinfo_arm_chipset_series_wondermedia_wm, 66*2b54f0dbSXin Li cpuinfo_arm_chipset_series_max, 67*2b54f0dbSXin Li }; 68*2b54f0dbSXin Li 69*2b54f0dbSXin Li #define CPUINFO_ARM_CHIPSET_SUFFIX_MAX 8 70*2b54f0dbSXin Li 71*2b54f0dbSXin Li struct cpuinfo_arm_chipset { 72*2b54f0dbSXin Li enum cpuinfo_arm_chipset_vendor vendor; 73*2b54f0dbSXin Li enum cpuinfo_arm_chipset_series series; 74*2b54f0dbSXin Li uint32_t model; 75*2b54f0dbSXin Li char suffix[CPUINFO_ARM_CHIPSET_SUFFIX_MAX]; 76*2b54f0dbSXin Li }; 77*2b54f0dbSXin Li 78*2b54f0dbSXin Li #define CPUINFO_ARM_CHIPSET_NAME_MAX CPUINFO_PACKAGE_NAME_MAX 79*2b54f0dbSXin Li 80*2b54f0dbSXin Li #ifndef __cplusplus 81*2b54f0dbSXin Li CPUINFO_INTERNAL void cpuinfo_arm_chipset_to_string( 82*2b54f0dbSXin Li const struct cpuinfo_arm_chipset chipset[restrict static 1], 83*2b54f0dbSXin Li char name[restrict static CPUINFO_ARM_CHIPSET_NAME_MAX]); 84*2b54f0dbSXin Li 85*2b54f0dbSXin Li CPUINFO_INTERNAL void cpuinfo_arm_fixup_chipset( 86*2b54f0dbSXin Li struct cpuinfo_arm_chipset chipset[restrict static 1], uint32_t cores, uint32_t max_cpu_freq_max); 87*2b54f0dbSXin Li 88*2b54f0dbSXin Li CPUINFO_INTERNAL void cpuinfo_arm_decode_vendor_uarch( 89*2b54f0dbSXin Li uint32_t midr, 90*2b54f0dbSXin Li #if CPUINFO_ARCH_ARM 91*2b54f0dbSXin Li bool has_vfpv4, 92*2b54f0dbSXin Li #endif 93*2b54f0dbSXin Li enum cpuinfo_vendor vendor[restrict static 1], 94*2b54f0dbSXin Li enum cpuinfo_uarch uarch[restrict static 1]); 95*2b54f0dbSXin Li 96*2b54f0dbSXin Li CPUINFO_INTERNAL void cpuinfo_arm_decode_cache( 97*2b54f0dbSXin Li enum cpuinfo_uarch uarch, 98*2b54f0dbSXin Li uint32_t cluster_cores, 99*2b54f0dbSXin Li uint32_t midr, 100*2b54f0dbSXin Li const struct cpuinfo_arm_chipset chipset[restrict static 1], 101*2b54f0dbSXin Li uint32_t cluster_id, 102*2b54f0dbSXin Li uint32_t arch_version, 103*2b54f0dbSXin Li struct cpuinfo_cache l1i[restrict static 1], 104*2b54f0dbSXin Li struct cpuinfo_cache l1d[restrict static 1], 105*2b54f0dbSXin Li struct cpuinfo_cache l2[restrict static 1], 106*2b54f0dbSXin Li struct cpuinfo_cache l3[restrict static 1]); 107*2b54f0dbSXin Li 108*2b54f0dbSXin Li CPUINFO_INTERNAL uint32_t cpuinfo_arm_compute_max_cache_size( 109*2b54f0dbSXin Li const struct cpuinfo_processor processor[restrict static 1]); 110*2b54f0dbSXin Li #else /* defined(__cplusplus) */ 111*2b54f0dbSXin Li CPUINFO_INTERNAL void cpuinfo_arm_decode_cache( 112*2b54f0dbSXin Li enum cpuinfo_uarch uarch, 113*2b54f0dbSXin Li uint32_t cluster_cores, 114*2b54f0dbSXin Li uint32_t midr, 115*2b54f0dbSXin Li const struct cpuinfo_arm_chipset chipset[1], 116*2b54f0dbSXin Li uint32_t cluster_id, 117*2b54f0dbSXin Li uint32_t arch_version, 118*2b54f0dbSXin Li struct cpuinfo_cache l1i[1], 119*2b54f0dbSXin Li struct cpuinfo_cache l1d[1], 120*2b54f0dbSXin Li struct cpuinfo_cache l2[1], 121*2b54f0dbSXin Li struct cpuinfo_cache l3[1]); 122*2b54f0dbSXin Li #endif 123