xref: /aosp_15_r20/external/cpu_features/test/cpuinfo_loongarch_test.cc (revision eca53ba6d2e951e174b64682eaf56a36b8204c89)
1*eca53ba6SRoland Levillain // Copyright 2022 Google LLC
2*eca53ba6SRoland Levillain //
3*eca53ba6SRoland Levillain // Licensed under the Apache License, Version 2.0 (the "License");
4*eca53ba6SRoland Levillain // you may not use this file except in compliance with the License.
5*eca53ba6SRoland Levillain // You may obtain a copy of the License at
6*eca53ba6SRoland Levillain //
7*eca53ba6SRoland Levillain //    http://www.apache.org/licenses/LICENSE-2.0
8*eca53ba6SRoland Levillain //
9*eca53ba6SRoland Levillain // Unless required by applicable law or agreed to in writing, software
10*eca53ba6SRoland Levillain // distributed under the License is distributed on an "AS IS" BASIS,
11*eca53ba6SRoland Levillain // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12*eca53ba6SRoland Levillain // See the License for the specific language governing permissions and
13*eca53ba6SRoland Levillain // limitations under the License.
14*eca53ba6SRoland Levillain 
15*eca53ba6SRoland Levillain #include "cpuinfo_loongarch.h"
16*eca53ba6SRoland Levillain 
17*eca53ba6SRoland Levillain #include "filesystem_for_testing.h"
18*eca53ba6SRoland Levillain #include "gtest/gtest.h"
19*eca53ba6SRoland Levillain #include "hwcaps_for_testing.h"
20*eca53ba6SRoland Levillain 
21*eca53ba6SRoland Levillain namespace cpu_features {
22*eca53ba6SRoland Levillain namespace {
23*eca53ba6SRoland Levillain 
TEST(CpuinfoLoongArchvTest,UnknownFromCpuInfo)24*eca53ba6SRoland Levillain TEST(CpuinfoLoongArchvTest, UnknownFromCpuInfo) {
25*eca53ba6SRoland Levillain   ResetHwcaps();
26*eca53ba6SRoland Levillain   auto& fs = GetEmptyFilesystem();
27*eca53ba6SRoland Levillain   fs.CreateFile("/proc/cpuinfo", R"(
28*eca53ba6SRoland Levillain system type		: generic-loongson-machine
29*eca53ba6SRoland Levillain 
30*eca53ba6SRoland Levillain processor		: 0
31*eca53ba6SRoland Levillain package			: 0
32*eca53ba6SRoland Levillain core			: 0
33*eca53ba6SRoland Levillain CPU Family		: Loongson-64bit
34*eca53ba6SRoland Levillain Model Name		: Loongson-3A5000-HV
35*eca53ba6SRoland Levillain CPU Revision		: 0x11
36*eca53ba6SRoland Levillain FPU Revision		: 0x00
37*eca53ba6SRoland Levillain CPU MHz			: 2500.00
38*eca53ba6SRoland Levillain BogoMIPS		: 5000.00
39*eca53ba6SRoland Levillain TLB Entries		: 2112
40*eca53ba6SRoland Levillain Address Sizes		: 48 bits physical, 48 bits virtual
41*eca53ba6SRoland Levillain ISA			: loongarch32 loongarch64
42*eca53ba6SRoland Levillain Features		: cpucfg lam ual fpu lsx lasx crc32 complex crypto lvz lbt_x86 lbt_arm lbt_mips
43*eca53ba6SRoland Levillain Hardware Watchpoint	: yes, iwatch count: 8, dwatch count: 8
44*eca53ba6SRoland Levillain 
45*eca53ba6SRoland Levillain processor		: 1
46*eca53ba6SRoland Levillain package			: 0
47*eca53ba6SRoland Levillain core			: 1
48*eca53ba6SRoland Levillain CPU Family		: Loongson-64bit
49*eca53ba6SRoland Levillain Model Name		: Loongson-3A5000-HV
50*eca53ba6SRoland Levillain CPU Revision		: 0x11
51*eca53ba6SRoland Levillain FPU Revision		: 0x00
52*eca53ba6SRoland Levillain CPU MHz			: 2500.00
53*eca53ba6SRoland Levillain BogoMIPS		: 5000.00
54*eca53ba6SRoland Levillain TLB Entries		: 2112
55*eca53ba6SRoland Levillain Address Sizes		: 48 bits physical, 48 bits virtual
56*eca53ba6SRoland Levillain ISA			: loongarch32 loongarch64
57*eca53ba6SRoland Levillain Features		: cpucfg lam ual fpu lsx lasx crc32 complex crypto lvz lbt_x86 lbt_arm lbt_mips
58*eca53ba6SRoland Levillain Hardware Watchpoint	: yes, iwatch count: 8, dwatch count: 8
59*eca53ba6SRoland Levillain 
60*eca53ba6SRoland Levillain processor		: 2
61*eca53ba6SRoland Levillain package			: 0
62*eca53ba6SRoland Levillain core			: 2
63*eca53ba6SRoland Levillain CPU Family		: Loongson-64bit
64*eca53ba6SRoland Levillain Model Name		: Loongson-3A5000-HV
65*eca53ba6SRoland Levillain CPU Revision		: 0x11
66*eca53ba6SRoland Levillain FPU Revision		: 0x00
67*eca53ba6SRoland Levillain CPU MHz			: 2500.00
68*eca53ba6SRoland Levillain BogoMIPS		: 5000.00
69*eca53ba6SRoland Levillain TLB Entries		: 2112
70*eca53ba6SRoland Levillain Address Sizes		: 48 bits physical, 48 bits virtual
71*eca53ba6SRoland Levillain ISA			: loongarch32 loongarch64
72*eca53ba6SRoland Levillain Features		: cpucfg lam ual fpu lsx lasx crc32 complex crypto lvz lbt_x86 lbt_arm lbt_mips
73*eca53ba6SRoland Levillain Hardware Watchpoint	: yes, iwatch count: 8, dwatch count: 8
74*eca53ba6SRoland Levillain 
75*eca53ba6SRoland Levillain processor		: 3
76*eca53ba6SRoland Levillain package			: 0
77*eca53ba6SRoland Levillain core			: 3
78*eca53ba6SRoland Levillain CPU Family		: Loongson-64bit
79*eca53ba6SRoland Levillain Model Name		: Loongson-3A5000-HV
80*eca53ba6SRoland Levillain CPU Revision		: 0x11
81*eca53ba6SRoland Levillain FPU Revision		: 0x00
82*eca53ba6SRoland Levillain CPU MHz			: 2500.00
83*eca53ba6SRoland Levillain BogoMIPS		: 5000.00
84*eca53ba6SRoland Levillain TLB Entries		: 2112
85*eca53ba6SRoland Levillain Address Sizes		: 48 bits physical, 48 bits virtual
86*eca53ba6SRoland Levillain ISA			: loongarch32 loongarch64
87*eca53ba6SRoland Levillain Features		: cpucfg lam ual fpu lsx lasx crc32 complex crypto lvz lbt_x86 lbt_arm lbt_mips
88*eca53ba6SRoland Levillain Hardware Watchpoint	: yes, iwatch count: 8, dwatch count: 8)");
89*eca53ba6SRoland Levillain   const auto info = GetLoongArchInfo();
90*eca53ba6SRoland Levillain   EXPECT_FALSE(info.features.CPUCFG);
91*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.LAM);
92*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.UAL);
93*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.FPU);
94*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.LSX);
95*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.LASX);
96*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.CRC32);
97*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.COMPLEX);
98*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.CRYPTO);
99*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.LVZ);
100*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.LBT_X86);
101*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.LBT_ARM);
102*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.LBT_MIPS);
103*eca53ba6SRoland Levillain }
104*eca53ba6SRoland Levillain 
TEST(CpuinfoLoongArchvTest,QemuCpuInfo)105*eca53ba6SRoland Levillain TEST(CpuinfoLoongArchvTest, QemuCpuInfo) {
106*eca53ba6SRoland Levillain   ResetHwcaps();
107*eca53ba6SRoland Levillain   auto& fs = GetEmptyFilesystem();
108*eca53ba6SRoland Levillain   fs.CreateFile("/proc/cpuinfo", R"(
109*eca53ba6SRoland Levillain system type		: generic-loongson-machine
110*eca53ba6SRoland Levillain 
111*eca53ba6SRoland Levillain processor		: 0
112*eca53ba6SRoland Levillain package			: 0
113*eca53ba6SRoland Levillain core			: 0
114*eca53ba6SRoland Levillain CPU Family		: Loongson-64bit
115*eca53ba6SRoland Levillain Model Name		: Loongson-3A5000
116*eca53ba6SRoland Levillain CPU Revision		: 0x10
117*eca53ba6SRoland Levillain FPU Revision		: 0x01
118*eca53ba6SRoland Levillain CPU MHz			: 2000.00
119*eca53ba6SRoland Levillain BogoMIPS		: 4000.00
120*eca53ba6SRoland Levillain TLB Entries		: 2112
121*eca53ba6SRoland Levillain Address Sizes		: 48 bits physical, 48 bits virtual
122*eca53ba6SRoland Levillain ISA			: loongarch32 loongarch64
123*eca53ba6SRoland Levillain Features		: cpucfg lam ual fpu crc32
124*eca53ba6SRoland Levillain Hardware Watchpoint	: yes, iwatch count: 0, dwatch count: 0
125*eca53ba6SRoland Levillain 
126*eca53ba6SRoland Levillain processor		: 1
127*eca53ba6SRoland Levillain package			: 0
128*eca53ba6SRoland Levillain core			: 1
129*eca53ba6SRoland Levillain CPU Family		: Loongson-64bit
130*eca53ba6SRoland Levillain Model Name		: Loongson-3A5000
131*eca53ba6SRoland Levillain CPU Revision		: 0x10
132*eca53ba6SRoland Levillain FPU Revision		: 0x01
133*eca53ba6SRoland Levillain CPU MHz			: 2000.00
134*eca53ba6SRoland Levillain BogoMIPS		: 4000.00
135*eca53ba6SRoland Levillain TLB Entries		: 2112
136*eca53ba6SRoland Levillain Address Sizes		: 48 bits physical, 48 bits virtual
137*eca53ba6SRoland Levillain ISA			: loongarch32 loongarch64
138*eca53ba6SRoland Levillain Features		: cpucfg lam ual fpu crc32
139*eca53ba6SRoland Levillain Hardware Watchpoint	: yes, iwatch count: 0, dwatch count: 0
140*eca53ba6SRoland Levillain 
141*eca53ba6SRoland Levillain processor		: 2
142*eca53ba6SRoland Levillain package			: 0
143*eca53ba6SRoland Levillain core			: 2
144*eca53ba6SRoland Levillain CPU Family		: Loongson-64bit
145*eca53ba6SRoland Levillain Model Name		: Loongson-3A5000
146*eca53ba6SRoland Levillain CPU Revision		: 0x10
147*eca53ba6SRoland Levillain FPU Revision		: 0x01
148*eca53ba6SRoland Levillain CPU MHz			: 2000.00
149*eca53ba6SRoland Levillain BogoMIPS		: 4000.00
150*eca53ba6SRoland Levillain TLB Entries		: 2112
151*eca53ba6SRoland Levillain Address Sizes		: 48 bits physical, 48 bits virtual
152*eca53ba6SRoland Levillain ISA			: loongarch32 loongarch64
153*eca53ba6SRoland Levillain Features		: cpucfg lam ual fpu crc32
154*eca53ba6SRoland Levillain Hardware Watchpoint	: yes, iwatch count: 0, dwatch count: 0
155*eca53ba6SRoland Levillain 
156*eca53ba6SRoland Levillain processor		: 3
157*eca53ba6SRoland Levillain package			: 0
158*eca53ba6SRoland Levillain core			: 3
159*eca53ba6SRoland Levillain CPU Family		: Loongson-64bit
160*eca53ba6SRoland Levillain Model Name		: Loongson-3A5000
161*eca53ba6SRoland Levillain CPU Revision		: 0x10
162*eca53ba6SRoland Levillain FPU Revision		: 0x01
163*eca53ba6SRoland Levillain CPU MHz			: 2000.00
164*eca53ba6SRoland Levillain BogoMIPS		: 4000.00
165*eca53ba6SRoland Levillain TLB Entries		: 2112
166*eca53ba6SRoland Levillain Address Sizes		: 48 bits physical, 48 bits virtual
167*eca53ba6SRoland Levillain ISA			: loongarch32 loongarch64
168*eca53ba6SRoland Levillain Features		: cpucfg lam ual fpu crc32
169*eca53ba6SRoland Levillain Hardware Watchpoint	: yes, iwatch count: 0, dwatch count: 0)");
170*eca53ba6SRoland Levillain   const auto info = GetLoongArchInfo();
171*eca53ba6SRoland Levillain   EXPECT_FALSE(info.features.CPUCFG);
172*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.LAM);
173*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.UAL);
174*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.FPU);
175*eca53ba6SRoland Levillain   EXPECT_TRUE(info.features.CRC32);
176*eca53ba6SRoland Levillain }
177*eca53ba6SRoland Levillain 
178*eca53ba6SRoland Levillain }  // namespace
179*eca53ba6SRoland Levillain }  // namespace cpu_features
180