1 // Copyright 2017 Google LLC 2 // Copyright 2020 Intel Corporation 3 // 4 // Licensed under the Apache License, Version 2.0 (the "License"); 5 // you may not use this file except in compliance with the License. 6 // You may obtain a copy of the License at 7 // 8 // http://www.apache.org/licenses/LICENSE-2.0 9 // 10 // Unless required by applicable law or agreed to in writing, software 11 // distributed under the License is distributed on an "AS IS" BASIS, 12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 // See the License for the specific language governing permissions and 14 // limitations under the License. 15 16 #ifndef CPU_FEATURES_INCLUDE_CPUINFO_X86_H_ 17 #define CPU_FEATURES_INCLUDE_CPUINFO_X86_H_ 18 19 #include "cpu_features_cache_info.h" 20 #include "cpu_features_macros.h" 21 22 CPU_FEATURES_START_CPP_NAMESPACE 23 24 // CPUID Vendors 25 #define CPU_FEATURES_VENDOR_GENUINE_INTEL "GenuineIntel" 26 #define CPU_FEATURES_VENDOR_AUTHENTIC_AMD "AuthenticAMD" 27 #define CPU_FEATURES_VENDOR_HYGON_GENUINE "HygonGenuine" 28 #define CPU_FEATURES_VENDOR_CENTAUR_HAULS "CentaurHauls" 29 #define CPU_FEATURES_VENDOR_SHANGHAI " Shanghai " 30 31 // See https://en.wikipedia.org/wiki/CPUID for a list of x86 cpu features. 32 // The field names are based on the short name provided in the wikipedia tables. 33 typedef struct { 34 int fpu : 1; 35 int tsc : 1; 36 int cx8 : 1; 37 int clfsh : 1; 38 int mmx : 1; 39 int aes : 1; 40 int erms : 1; 41 int f16c : 1; 42 int fma4 : 1; 43 int fma3 : 1; 44 int vaes : 1; 45 int vpclmulqdq : 1; 46 int bmi1 : 1; 47 int hle : 1; 48 int bmi2 : 1; 49 int rtm : 1; 50 int rdseed : 1; 51 int clflushopt : 1; 52 int clwb : 1; 53 54 int sse : 1; 55 int sse2 : 1; 56 int sse3 : 1; 57 int ssse3 : 1; 58 int sse4_1 : 1; 59 int sse4_2 : 1; 60 int sse4a : 1; 61 62 int avx : 1; 63 int avx_vnni : 1; 64 int avx2 : 1; 65 66 int avx512f : 1; 67 int avx512cd : 1; 68 int avx512er : 1; 69 int avx512pf : 1; 70 int avx512bw : 1; 71 int avx512dq : 1; 72 int avx512vl : 1; 73 int avx512ifma : 1; 74 int avx512vbmi : 1; 75 int avx512vbmi2 : 1; 76 int avx512vnni : 1; 77 int avx512bitalg : 1; 78 int avx512vpopcntdq : 1; 79 int avx512_4vnniw : 1; 80 int avx512_4vbmi2 : 1; // Note: this is an alias to avx512_4fmaps. 81 int avx512_second_fma : 1; 82 int avx512_4fmaps : 1; 83 int avx512_bf16 : 1; 84 int avx512_vp2intersect : 1; 85 int avx512_fp16 : 1; 86 int amx_bf16 : 1; 87 int amx_tile : 1; 88 int amx_int8 : 1; 89 int amx_fp16 : 1; 90 91 int pclmulqdq : 1; 92 int smx : 1; 93 int sgx : 1; 94 int cx16 : 1; // aka. CMPXCHG16B 95 int sha : 1; 96 int popcnt : 1; 97 int movbe : 1; 98 int rdrnd : 1; 99 100 int dca : 1; 101 int ss : 1; 102 int adx : 1; 103 int lzcnt : 1; // Note: this flag is called ABM for AMD, LZCNT for Intel. 104 int gfni : 1; 105 int movdiri : 1; 106 int movdir64b : 1; 107 int fs_rep_mov : 1; // Fast short REP MOV 108 int fz_rep_movsb : 1; // Fast zero-length REP MOVSB 109 int fs_rep_stosb : 1; // Fast short REP STOSB 110 int fs_rep_cmpsb_scasb : 1; // Fast short REP CMPSB/SCASB 111 112 int lam: 1; // Intel Linear Address Mask 113 int uai: 1; // AMD Upper Address Ignore 114 // Make sure to update X86FeaturesEnum below if you add a field here. 115 } X86Features; 116 117 typedef struct { 118 X86Features features; 119 int family; 120 int model; 121 int stepping; 122 char vendor[13]; // 0 terminated string 123 char brand_string[49]; // 0 terminated string 124 } X86Info; 125 126 // Calls cpuid and returns an initialized X86info. 127 X86Info GetX86Info(void); 128 129 // Returns cache hierarchy informations. 130 // Can call cpuid multiple times. 131 CacheInfo GetX86CacheInfo(void); 132 133 typedef enum { 134 X86_UNKNOWN, 135 ZHAOXIN_ZHANGJIANG, // ZhangJiang 136 ZHAOXIN_WUDAOKOU, // WuDaoKou 137 ZHAOXIN_LUJIAZUI, // LuJiaZui 138 ZHAOXIN_YONGFENG, // YongFeng 139 INTEL_80486, // 80486 140 INTEL_P5, // P5 141 INTEL_LAKEMONT, // LAKEMONT 142 INTEL_CORE, // CORE 143 INTEL_PNR, // PENRYN 144 INTEL_NHM, // NEHALEM 145 INTEL_ATOM_BNL, // BONNELL 146 INTEL_WSM, // WESTMERE 147 INTEL_SNB, // SANDYBRIDGE 148 INTEL_IVB, // IVYBRIDGE 149 INTEL_ATOM_SMT, // SILVERMONT 150 INTEL_HSW, // HASWELL 151 INTEL_BDW, // BROADWELL 152 INTEL_SKL, // SKYLAKE 153 INTEL_CCL, // CASCADELAKE 154 INTEL_ATOM_GMT, // GOLDMONT 155 INTEL_ATOM_GMT_PLUS, // GOLDMONT+ 156 INTEL_ATOM_TMT, // TREMONT 157 INTEL_KBL, // KABY LAKE 158 INTEL_CFL, // COFFEE LAKE 159 INTEL_WHL, // WHISKEY LAKE 160 INTEL_CML, // COMET LAKE 161 INTEL_CNL, // CANNON LAKE 162 INTEL_ICL, // ICE LAKE 163 INTEL_TGL, // TIGER LAKE 164 INTEL_SPR, // SAPPHIRE RAPIDS 165 INTEL_ADL, // ALDER LAKE 166 INTEL_RCL, // ROCKET LAKE 167 INTEL_RPL, // RAPTOR LAKE 168 INTEL_KNIGHTS_M, // KNIGHTS MILL 169 INTEL_KNIGHTS_L, // KNIGHTS LANDING 170 INTEL_KNIGHTS_F, // KNIGHTS FERRY 171 INTEL_KNIGHTS_C, // KNIGHTS CORNER 172 INTEL_NETBURST, // NETBURST 173 AMD_HAMMER, // K8 HAMMER 174 AMD_K10, // K10 175 AMD_K11, // K11 176 AMD_K12, // K12 LLANO 177 AMD_BOBCAT, // K14 BOBCAT 178 AMD_PILEDRIVER, // K15 PILEDRIVER 179 AMD_STREAMROLLER, // K15 STREAMROLLER 180 AMD_EXCAVATOR, // K15 EXCAVATOR 181 AMD_BULLDOZER, // K15 BULLDOZER 182 AMD_JAGUAR, // K16 JAGUAR 183 AMD_PUMA, // K16 PUMA 184 AMD_ZEN, // K17 ZEN 185 AMD_ZEN_PLUS, // K17 ZEN+ 186 AMD_ZEN2, // K17 ZEN 2 187 AMD_ZEN3, // K19 ZEN 3 188 AMD_ZEN4, // K19 ZEN 4 189 X86_MICROARCHITECTURE_LAST_, 190 } X86Microarchitecture; 191 192 // Returns the underlying microarchitecture by looking at X86Info's vendor, 193 // family and model. 194 X86Microarchitecture GetX86Microarchitecture(const X86Info* info); 195 196 // Calls cpuid and fills the brand_string. 197 // - brand_string *must* be of size 49 (beware of array decaying). 198 // - brand_string will be zero terminated. 199 CPU_FEATURES_DEPRECATED("brand_string is now embedded in X86Info by default") 200 void FillX86BrandString(char brand_string[49]); 201 202 //////////////////////////////////////////////////////////////////////////////// 203 // Introspection functions 204 205 typedef enum { 206 X86_FPU, 207 X86_TSC, 208 X86_CX8, 209 X86_CLFSH, 210 X86_MMX, 211 X86_AES, 212 X86_ERMS, 213 X86_F16C, 214 X86_FMA4, 215 X86_FMA3, 216 X86_VAES, 217 X86_VPCLMULQDQ, 218 X86_BMI1, 219 X86_HLE, 220 X86_BMI2, 221 X86_RTM, 222 X86_RDSEED, 223 X86_CLFLUSHOPT, 224 X86_CLWB, 225 X86_SSE, 226 X86_SSE2, 227 X86_SSE3, 228 X86_SSSE3, 229 X86_SSE4_1, 230 X86_SSE4_2, 231 X86_SSE4A, 232 X86_AVX, 233 X86_AVX_VNNI, 234 X86_AVX2, 235 X86_AVX512F, 236 X86_AVX512CD, 237 X86_AVX512ER, 238 X86_AVX512PF, 239 X86_AVX512BW, 240 X86_AVX512DQ, 241 X86_AVX512VL, 242 X86_AVX512IFMA, 243 X86_AVX512VBMI, 244 X86_AVX512VBMI2, 245 X86_AVX512VNNI, 246 X86_AVX512BITALG, 247 X86_AVX512VPOPCNTDQ, 248 X86_AVX512_4VNNIW, 249 X86_AVX512_4VBMI2, // Note: this is an alias to X86_AVX512_4FMAPS. 250 X86_AVX512_SECOND_FMA, 251 X86_AVX512_4FMAPS, 252 X86_AVX512_BF16, 253 X86_AVX512_VP2INTERSECT, 254 X86_AVX512_FP16, 255 X86_AMX_BF16, 256 X86_AMX_TILE, 257 X86_AMX_INT8, 258 X86_AMX_FP16, 259 X86_PCLMULQDQ, 260 X86_SMX, 261 X86_SGX, 262 X86_CX16, 263 X86_SHA, 264 X86_POPCNT, 265 X86_MOVBE, 266 X86_RDRND, 267 X86_DCA, 268 X86_SS, 269 X86_ADX, 270 X86_LZCNT, 271 X86_GFNI, 272 X86_MOVDIRI, 273 X86_MOVDIR64B, 274 X86_FS_REP_MOV, 275 X86_FZ_REP_MOVSB, 276 X86_FS_REP_STOSB, 277 X86_FS_REP_CMPSB_SCASB, 278 X86_LAM, 279 X86_UAI, 280 X86_LAST_, 281 } X86FeaturesEnum; 282 283 int GetX86FeaturesEnumValue(const X86Features* features, X86FeaturesEnum value); 284 285 const char* GetX86FeaturesEnumName(X86FeaturesEnum); 286 287 const char* GetX86MicroarchitectureName(X86Microarchitecture); 288 289 CPU_FEATURES_END_CPP_NAMESPACE 290 291 #if !defined(CPU_FEATURES_ARCH_X86) 292 #error "Including cpuinfo_x86.h from a non-x86 target." 293 #endif 294 295 #endif // CPU_FEATURES_INCLUDE_CPUINFO_X86_H_ 296