1*eca53ba6SRoland Levillain // Copyright 2017 Google LLC 2*eca53ba6SRoland Levillain // 3*eca53ba6SRoland Levillain // Licensed under the Apache License, Version 2.0 (the "License"); 4*eca53ba6SRoland Levillain // you may not use this file except in compliance with the License. 5*eca53ba6SRoland Levillain // You may obtain a copy of the License at 6*eca53ba6SRoland Levillain // 7*eca53ba6SRoland Levillain // http://www.apache.org/licenses/LICENSE-2.0 8*eca53ba6SRoland Levillain // 9*eca53ba6SRoland Levillain // Unless required by applicable law or agreed to in writing, software 10*eca53ba6SRoland Levillain // distributed under the License is distributed on an "AS IS" BASIS, 11*eca53ba6SRoland Levillain // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12*eca53ba6SRoland Levillain // See the License for the specific language governing permissions and 13*eca53ba6SRoland Levillain // limitations under the License. 14*eca53ba6SRoland Levillain 15*eca53ba6SRoland Levillain #ifndef CPU_FEATURES_INCLUDE_CPU_FEATURES_MACROS_H_ 16*eca53ba6SRoland Levillain #define CPU_FEATURES_INCLUDE_CPU_FEATURES_MACROS_H_ 17*eca53ba6SRoland Levillain 18*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 19*eca53ba6SRoland Levillain // Architectures 20*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 21*eca53ba6SRoland Levillain 22*eca53ba6SRoland Levillain #if defined(__pnacl__) || defined(__CLR_VER) 23*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_VM 24*eca53ba6SRoland Levillain #endif 25*eca53ba6SRoland Levillain 26*eca53ba6SRoland Levillain #if (defined(_M_IX86) || defined(__i386__)) && !defined(CPU_FEATURES_ARCH_VM) 27*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_X86_32 28*eca53ba6SRoland Levillain #endif 29*eca53ba6SRoland Levillain 30*eca53ba6SRoland Levillain #if (defined(_M_X64) || defined(__x86_64__)) && !defined(CPU_FEATURES_ARCH_VM) 31*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_X86_64 32*eca53ba6SRoland Levillain #endif 33*eca53ba6SRoland Levillain 34*eca53ba6SRoland Levillain #if defined(CPU_FEATURES_ARCH_X86_32) || defined(CPU_FEATURES_ARCH_X86_64) 35*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_X86 36*eca53ba6SRoland Levillain #endif 37*eca53ba6SRoland Levillain 38*eca53ba6SRoland Levillain #if (defined(__arm__) || defined(_M_ARM)) 39*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_ARM 40*eca53ba6SRoland Levillain #endif 41*eca53ba6SRoland Levillain 42*eca53ba6SRoland Levillain #if (defined(__aarch64__) || defined(_M_ARM64)) 43*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_AARCH64 44*eca53ba6SRoland Levillain #endif 45*eca53ba6SRoland Levillain 46*eca53ba6SRoland Levillain #if (defined(CPU_FEATURES_ARCH_AARCH64) || defined(CPU_FEATURES_ARCH_ARM)) 47*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_ANY_ARM 48*eca53ba6SRoland Levillain #endif 49*eca53ba6SRoland Levillain 50*eca53ba6SRoland Levillain #if defined(__mips64) 51*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_MIPS64 52*eca53ba6SRoland Levillain #endif 53*eca53ba6SRoland Levillain 54*eca53ba6SRoland Levillain #if defined(__mips__) && !defined(__mips64) // mips64 also declares __mips__ 55*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_MIPS32 56*eca53ba6SRoland Levillain #endif 57*eca53ba6SRoland Levillain 58*eca53ba6SRoland Levillain #if defined(CPU_FEATURES_ARCH_MIPS32) || defined(CPU_FEATURES_ARCH_MIPS64) 59*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_MIPS 60*eca53ba6SRoland Levillain #endif 61*eca53ba6SRoland Levillain 62*eca53ba6SRoland Levillain #if defined(__powerpc__) 63*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_PPC 64*eca53ba6SRoland Levillain #endif 65*eca53ba6SRoland Levillain 66*eca53ba6SRoland Levillain #if defined(__s390x__) 67*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_S390X 68*eca53ba6SRoland Levillain #endif 69*eca53ba6SRoland Levillain 70*eca53ba6SRoland Levillain #if defined(__riscv) 71*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_RISCV 72*eca53ba6SRoland Levillain #endif 73*eca53ba6SRoland Levillain 74*eca53ba6SRoland Levillain #if defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 32 75*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_RISCV32 76*eca53ba6SRoland Levillain #endif 77*eca53ba6SRoland Levillain 78*eca53ba6SRoland Levillain #if defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64 79*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_RISCV64 80*eca53ba6SRoland Levillain #endif 81*eca53ba6SRoland Levillain 82*eca53ba6SRoland Levillain #if defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 128 83*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_RISCV128 84*eca53ba6SRoland Levillain #endif 85*eca53ba6SRoland Levillain 86*eca53ba6SRoland Levillain #if defined(__loongarch64) 87*eca53ba6SRoland Levillain #define CPU_FEATURES_ARCH_LOONGARCH 88*eca53ba6SRoland Levillain #endif 89*eca53ba6SRoland Levillain 90*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 91*eca53ba6SRoland Levillain // Os 92*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 93*eca53ba6SRoland Levillain 94*eca53ba6SRoland Levillain #if (defined(__freebsd__) || defined(__FreeBSD__)) 95*eca53ba6SRoland Levillain #define CPU_FEATURES_OS_FREEBSD 96*eca53ba6SRoland Levillain #endif 97*eca53ba6SRoland Levillain 98*eca53ba6SRoland Levillain #if defined(__ANDROID__) 99*eca53ba6SRoland Levillain #define CPU_FEATURES_OS_ANDROID 100*eca53ba6SRoland Levillain #endif 101*eca53ba6SRoland Levillain 102*eca53ba6SRoland Levillain #if defined(__linux__) && !defined(CPU_FEATURES_OS_FREEBSD) && \ 103*eca53ba6SRoland Levillain !defined(CPU_FEATURES_OS_ANDROID) 104*eca53ba6SRoland Levillain #define CPU_FEATURES_OS_LINUX 105*eca53ba6SRoland Levillain #endif 106*eca53ba6SRoland Levillain 107*eca53ba6SRoland Levillain #if (defined(_WIN64) || defined(_WIN32)) 108*eca53ba6SRoland Levillain #define CPU_FEATURES_OS_WINDOWS 109*eca53ba6SRoland Levillain #endif 110*eca53ba6SRoland Levillain 111*eca53ba6SRoland Levillain #if (defined(__apple__) || defined(__APPLE__) || defined(__MACH__)) 112*eca53ba6SRoland Levillain // From https://stackoverflow.com/a/49560690 113*eca53ba6SRoland Levillain #include "TargetConditionals.h" 114*eca53ba6SRoland Levillain #if defined(TARGET_OS_OSX) 115*eca53ba6SRoland Levillain #define CPU_FEATURES_OS_MACOS 116*eca53ba6SRoland Levillain #endif 117*eca53ba6SRoland Levillain #if defined(TARGET_OS_IPHONE) 118*eca53ba6SRoland Levillain // This is set for any non-Mac Apple products (IOS, TV, WATCH) 119*eca53ba6SRoland Levillain #define CPU_FEATURES_OS_IPHONE 120*eca53ba6SRoland Levillain #endif 121*eca53ba6SRoland Levillain #endif 122*eca53ba6SRoland Levillain 123*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 124*eca53ba6SRoland Levillain // Compilers 125*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 126*eca53ba6SRoland Levillain 127*eca53ba6SRoland Levillain #if defined(__clang__) 128*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILER_CLANG 129*eca53ba6SRoland Levillain #endif 130*eca53ba6SRoland Levillain 131*eca53ba6SRoland Levillain #if defined(__GNUC__) && !defined(__clang__) 132*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILER_GCC 133*eca53ba6SRoland Levillain #endif 134*eca53ba6SRoland Levillain 135*eca53ba6SRoland Levillain #if defined(_MSC_VER) 136*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILER_MSC 137*eca53ba6SRoland Levillain #endif 138*eca53ba6SRoland Levillain 139*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 140*eca53ba6SRoland Levillain // Cpp 141*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 142*eca53ba6SRoland Levillain 143*eca53ba6SRoland Levillain #if defined(__cplusplus) 144*eca53ba6SRoland Levillain #define CPU_FEATURES_START_CPP_NAMESPACE \ 145*eca53ba6SRoland Levillain namespace cpu_features { \ 146*eca53ba6SRoland Levillain extern "C" { 147*eca53ba6SRoland Levillain #define CPU_FEATURES_END_CPP_NAMESPACE \ 148*eca53ba6SRoland Levillain } \ 149*eca53ba6SRoland Levillain } 150*eca53ba6SRoland Levillain #else 151*eca53ba6SRoland Levillain #define CPU_FEATURES_START_CPP_NAMESPACE 152*eca53ba6SRoland Levillain #define CPU_FEATURES_END_CPP_NAMESPACE 153*eca53ba6SRoland Levillain #endif 154*eca53ba6SRoland Levillain 155*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 156*eca53ba6SRoland Levillain // Compiler flags 157*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 158*eca53ba6SRoland Levillain 159*eca53ba6SRoland Levillain // Use the following to check if a feature is known to be available at 160*eca53ba6SRoland Levillain // compile time. See README.md for an example. 161*eca53ba6SRoland Levillain #if defined(CPU_FEATURES_ARCH_X86) 162*eca53ba6SRoland Levillain 163*eca53ba6SRoland Levillain #if defined(__AES__) 164*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_AES 1 165*eca53ba6SRoland Levillain #else 166*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_AES 0 167*eca53ba6SRoland Levillain #endif // defined(__AES__) 168*eca53ba6SRoland Levillain 169*eca53ba6SRoland Levillain #if defined(__F16C__) 170*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_F16C 1 171*eca53ba6SRoland Levillain #else 172*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_F16C 0 173*eca53ba6SRoland Levillain #endif // defined(__F16C__) 174*eca53ba6SRoland Levillain 175*eca53ba6SRoland Levillain #if defined(__BMI__) 176*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_BMI 1 177*eca53ba6SRoland Levillain #else 178*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_BMI 0 179*eca53ba6SRoland Levillain #endif // defined(__BMI__) 180*eca53ba6SRoland Levillain 181*eca53ba6SRoland Levillain #if defined(__BMI2__) 182*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_BMI2 1 183*eca53ba6SRoland Levillain #else 184*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_BMI2 0 185*eca53ba6SRoland Levillain #endif // defined(__BMI2__) 186*eca53ba6SRoland Levillain 187*eca53ba6SRoland Levillain #if (defined(__SSE__) || (_M_IX86_FP >= 1)) 188*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSE 1 189*eca53ba6SRoland Levillain #else 190*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSE 0 191*eca53ba6SRoland Levillain #endif 192*eca53ba6SRoland Levillain 193*eca53ba6SRoland Levillain #if (defined(__SSE2__) || (_M_IX86_FP >= 2)) 194*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSE2 1 195*eca53ba6SRoland Levillain #else 196*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSE2 0 197*eca53ba6SRoland Levillain #endif 198*eca53ba6SRoland Levillain 199*eca53ba6SRoland Levillain #if defined(__SSE3__) 200*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSE3 1 201*eca53ba6SRoland Levillain #else 202*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSE3 0 203*eca53ba6SRoland Levillain #endif // defined(__SSE3__) 204*eca53ba6SRoland Levillain 205*eca53ba6SRoland Levillain #if defined(__SSSE3__) 206*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSSE3 1 207*eca53ba6SRoland Levillain #else 208*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSSE3 0 209*eca53ba6SRoland Levillain #endif // defined(__SSSE3__) 210*eca53ba6SRoland Levillain 211*eca53ba6SRoland Levillain #if defined(__SSE4_1__) 212*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSE4_1 1 213*eca53ba6SRoland Levillain #else 214*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSE4_1 0 215*eca53ba6SRoland Levillain #endif // defined(__SSE4_1__) 216*eca53ba6SRoland Levillain 217*eca53ba6SRoland Levillain #if defined(__SSE4_2__) 218*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSE4_2 1 219*eca53ba6SRoland Levillain #else 220*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_SSE4_2 0 221*eca53ba6SRoland Levillain #endif // defined(__SSE4_2__) 222*eca53ba6SRoland Levillain 223*eca53ba6SRoland Levillain #if defined(__AVX__) 224*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_AVX 1 225*eca53ba6SRoland Levillain #else 226*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_AVX 0 227*eca53ba6SRoland Levillain #endif // defined(__AVX__) 228*eca53ba6SRoland Levillain 229*eca53ba6SRoland Levillain #if defined(__AVX2__) 230*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_AVX2 1 231*eca53ba6SRoland Levillain #else 232*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_X86_AVX2 0 233*eca53ba6SRoland Levillain #endif // defined(__AVX2__) 234*eca53ba6SRoland Levillain 235*eca53ba6SRoland Levillain #endif // defined(CPU_FEATURES_ARCH_X86) 236*eca53ba6SRoland Levillain 237*eca53ba6SRoland Levillain #if defined(CPU_FEATURES_ARCH_ANY_ARM) 238*eca53ba6SRoland Levillain #if defined(__ARM_NEON__) 239*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_ANY_ARM_NEON 1 240*eca53ba6SRoland Levillain #else 241*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_ANY_ARM_NEON 0 242*eca53ba6SRoland Levillain #endif // defined(__ARM_NEON__) 243*eca53ba6SRoland Levillain #endif // defined(CPU_FEATURES_ARCH_ANY_ARM) 244*eca53ba6SRoland Levillain 245*eca53ba6SRoland Levillain #if defined(CPU_FEATURES_ARCH_MIPS) 246*eca53ba6SRoland Levillain #if defined(__mips_msa) 247*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_MIPS_MSA 1 248*eca53ba6SRoland Levillain #else 249*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_MIPS_MSA 0 250*eca53ba6SRoland Levillain #endif // defined(__mips_msa) 251*eca53ba6SRoland Levillain #if defined(__mips3d) 252*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_MIPS_MIPS3D 1 253*eca53ba6SRoland Levillain #else 254*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_MIPS_MIPS3D 0 255*eca53ba6SRoland Levillain #endif 256*eca53ba6SRoland Levillain #endif // defined(CPU_FEATURES_ARCH_MIPS) 257*eca53ba6SRoland Levillain 258*eca53ba6SRoland Levillain #if defined(CPU_FEATURES_ARCH_RISCV) 259*eca53ba6SRoland Levillain #if defined(__riscv_e) 260*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_E 1 261*eca53ba6SRoland Levillain #else 262*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_E 0 263*eca53ba6SRoland Levillain #endif 264*eca53ba6SRoland Levillain #if defined(__riscv_i) 265*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_I 1 266*eca53ba6SRoland Levillain #else 267*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_I 0 268*eca53ba6SRoland Levillain #endif 269*eca53ba6SRoland Levillain #if defined(__riscv_m) 270*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_M 1 271*eca53ba6SRoland Levillain #else 272*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_M 0 273*eca53ba6SRoland Levillain #endif 274*eca53ba6SRoland Levillain #if defined(__riscv_a) 275*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_A 1 276*eca53ba6SRoland Levillain #else 277*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_A 0 278*eca53ba6SRoland Levillain #endif 279*eca53ba6SRoland Levillain #if defined(__riscv_f) 280*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_F 1 281*eca53ba6SRoland Levillain #else 282*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_F 0 283*eca53ba6SRoland Levillain #endif 284*eca53ba6SRoland Levillain #if defined(__riscv_d) 285*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_D 1 286*eca53ba6SRoland Levillain #else 287*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_D 0 288*eca53ba6SRoland Levillain #endif 289*eca53ba6SRoland Levillain #if defined(__riscv_q) 290*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_Q 1 291*eca53ba6SRoland Levillain #else 292*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_Q 0 293*eca53ba6SRoland Levillain #endif 294*eca53ba6SRoland Levillain #if defined(__riscv_c) 295*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_C 1 296*eca53ba6SRoland Levillain #else 297*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_C 0 298*eca53ba6SRoland Levillain #endif 299*eca53ba6SRoland Levillain #if defined(__riscv_v) 300*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_V 1 301*eca53ba6SRoland Levillain #else 302*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_V 0 303*eca53ba6SRoland Levillain #endif 304*eca53ba6SRoland Levillain #if defined(__riscv_zba) 305*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZBA 1 306*eca53ba6SRoland Levillain #else 307*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZBA 0 308*eca53ba6SRoland Levillain #endif 309*eca53ba6SRoland Levillain #if defined(__riscv_zbb) 310*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZBB 1 311*eca53ba6SRoland Levillain #else 312*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZBB 0 313*eca53ba6SRoland Levillain #endif 314*eca53ba6SRoland Levillain #if defined(__riscv_zbc) 315*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZBC 1 316*eca53ba6SRoland Levillain #else 317*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZBC 0 318*eca53ba6SRoland Levillain #endif 319*eca53ba6SRoland Levillain #if defined(__riscv_zbs) 320*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZBS 1 321*eca53ba6SRoland Levillain #else 322*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZBS 0 323*eca53ba6SRoland Levillain #endif 324*eca53ba6SRoland Levillain #if defined(__riscv_zfh) 325*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZFH 1 326*eca53ba6SRoland Levillain #else 327*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZFH 0 328*eca53ba6SRoland Levillain #endif 329*eca53ba6SRoland Levillain #if defined(__riscv_zfhmin) 330*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZFHMIN 1 331*eca53ba6SRoland Levillain #else 332*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZFHMIN 0 333*eca53ba6SRoland Levillain #endif 334*eca53ba6SRoland Levillain #if defined(__riscv_zknd) 335*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKND 1 336*eca53ba6SRoland Levillain #else 337*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKND 0 338*eca53ba6SRoland Levillain #endif 339*eca53ba6SRoland Levillain #if defined(__riscv_zkne) 340*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKNE 1 341*eca53ba6SRoland Levillain #else 342*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKNE 0 343*eca53ba6SRoland Levillain #endif 344*eca53ba6SRoland Levillain #if defined(__riscv_zknh) 345*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKNH 1 346*eca53ba6SRoland Levillain #else 347*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKNH 0 348*eca53ba6SRoland Levillain #endif 349*eca53ba6SRoland Levillain #if defined(__riscv_zksed) 350*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKSED 1 351*eca53ba6SRoland Levillain #else 352*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKSED 0 353*eca53ba6SRoland Levillain #endif 354*eca53ba6SRoland Levillain #if defined(__riscv_zksh) 355*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKSH 1 356*eca53ba6SRoland Levillain #else 357*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKSH 0 358*eca53ba6SRoland Levillain #endif 359*eca53ba6SRoland Levillain #if defined(__riscv_zkr) 360*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKR 1 361*eca53ba6SRoland Levillain #else 362*eca53ba6SRoland Levillain #define CPU_FEATURES_COMPILED_RISCV_ZKR 0 363*eca53ba6SRoland Levillain #endif 364*eca53ba6SRoland Levillain #endif // defined(CPU_FEATURES_ARCH_RISCV) 365*eca53ba6SRoland Levillain 366*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 367*eca53ba6SRoland Levillain // Utils 368*eca53ba6SRoland Levillain //////////////////////////////////////////////////////////////////////////////// 369*eca53ba6SRoland Levillain 370*eca53ba6SRoland Levillain // Communicates to the compiler that the block is unreachable 371*eca53ba6SRoland Levillain #if defined(CPU_FEATURES_COMPILER_CLANG) || defined(CPU_FEATURES_COMPILER_GCC) 372*eca53ba6SRoland Levillain #define CPU_FEATURES_UNREACHABLE() __builtin_unreachable() 373*eca53ba6SRoland Levillain #elif defined(CPU_FEATURES_COMPILER_MSC) 374*eca53ba6SRoland Levillain #define CPU_FEATURES_UNREACHABLE() __assume(0) 375*eca53ba6SRoland Levillain #else 376*eca53ba6SRoland Levillain #define CPU_FEATURES_UNREACHABLE() 377*eca53ba6SRoland Levillain #endif 378*eca53ba6SRoland Levillain 379*eca53ba6SRoland Levillain // Communicates to the compiler that the function is now deprecated 380*eca53ba6SRoland Levillain #if defined(CPU_FEATURES_COMPILER_CLANG) || defined(CPU_FEATURES_COMPILER_GCC) 381*eca53ba6SRoland Levillain #define CPU_FEATURES_DEPRECATED(message) __attribute__((deprecated(message))) 382*eca53ba6SRoland Levillain #elif defined(CPU_FEATURES_COMPILER_MSC) 383*eca53ba6SRoland Levillain #define CPU_FEATURES_DEPRECATED(message) __declspec(deprecated(message)) 384*eca53ba6SRoland Levillain #else 385*eca53ba6SRoland Levillain #define CPU_FEATURES_DEPRECATED(message) 386*eca53ba6SRoland Levillain #endif 387*eca53ba6SRoland Levillain 388*eca53ba6SRoland Levillain #endif // CPU_FEATURES_INCLUDE_CPU_FEATURES_MACROS_H_ 389