xref: /aosp_15_r20/external/coreboot/Documentation/mainboard/asrock/h77pro4-m.md (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1# ASRock H77 Pro4-M
2
3The ASRock H77 Pro4-M is a microATX-sized desktop board for Intel Sandy
4Bridge and Ivy Bridge CPUs.
5
6## Technology
7
8```{eval-rst}
9+------------------+--------------------------------------------------+
10| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
11+------------------+--------------------------------------------------+
12| Southbridge      | Intel H77 (bd82x6x)                              |
13+------------------+--------------------------------------------------+
14| CPU socket       | LGA 1155                                         |
15+------------------+--------------------------------------------------+
16| RAM              | 4 x DDR3-1600                                    |
17+------------------+--------------------------------------------------+
18| Super I/O        | Nuvoton NCT6776                                  |
19+------------------+--------------------------------------------------+
20| Audio            | Realtek ALC892                                   |
21+------------------+--------------------------------------------------+
22| Network          | Realtek RTL8111E                                 |
23+------------------+--------------------------------------------------+
24| Serial           | Internal header (RS-232)                         |
25+------------------+--------------------------------------------------+
26```
27
28## Status
29
30Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
31(linux-4.19.50).
32
33### Working
34
35- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
36- Native RAM initialization with four DIMMs
37- PS/2 combined port (mouse or keyboard)
38- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
39- PCIe graphics in the PEG slot
40- All three additional PCIe slots
41- All rear and internal USB2 ports
42- All rear and internal USB3 ports
43- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
44- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
45- Rear eSATA connector (multiplexed with one ASM1061 port)
46- Gigabit Ethernet
47- Console output on the serial port
48- EDK II (MrChromebox's fork, at origin/uefipayload_202207) to boot
49Windows 10 (22H2) and Linux (5.19.17) via GRUB 2
50- SeaBIOS 1.16.1 to boot Windows 10 (needs VGA BIOS) and Linux via
51extlinux
52- Internal flashing with flashrom-1.2, see
53[Internal Programming](#internal-programming)
54- External flashing with flashrom-1.2 and a Raspberry Pi 1
55- S3 suspend/resume from either Linux or Windows 10
56- Poweroff
57
58### Not working
59
60- Booting from the two SATA ports provided by the ASM1061
61- Automatic fan control with the NCT6776D Super I/O
62
63### Untested
64
65- EHCI debug
66- S/PDIF audio
67- Other audio jacks than the green one, and the front panel header
68- Parallel port
69- Infrared/CIR
70- Wakeup from anything but the power button
71
72## Flashing coreboot
73
74```{eval-rst}
75+---------------------+------------+
76| Type                | Value      |
77+=====================+============+
78| Socketed flash      | yes        |
79+---------------------+------------+
80| Model               | W25Q64.V   |
81+---------------------+------------+
82| Size                | 8 MiB      |
83+---------------------+------------+
84| Package             | DIP-8      |
85+---------------------+------------+
86| Write protection    | no         |
87+---------------------+------------+
88| Dual BIOS feature   | no         |
89+---------------------+------------+
90| Internal flashing   | yes        |
91+---------------------+------------+
92```
93
94The flash is divided into the following regions, as obtained with
95`ifdtool -f rom.layout backup.rom`:
96```
9700000000:00000fff fd
9800200000:007fffff bios
9900001000:001fffff me
100```
101
102### Internal programming
103
104The main SPI flash can be accessed using flashrom. By default, only
105the BIOS region of the flash is writable. If you wish to change any
106other region (Management Engine or flash descriptor), then an external
107programmer is required.
108
109The following command may be used to flash coreboot:
110
111```
112$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
113```
114
115The use of `--noverify-all` is required since the Management Engine
116region is not readable even by the host.
117
118```{eval-rst}
119In addition to the information here, please see the
120:doc:`../../tutorial/flashing_firmware/index`.
121```
122
123## Hardware monitoring and fan control
124
125There are two fan headers for the CPU cooler, CPU_FAN1 and CPU_FAN2. They share
126a single fan tachometer input on the Super I/O while some dedicated logic
127selects which one is allowed to reach it. Two GPIO pins on the Super I/O are
128used to control that logic. The firmware has to set them; coreboot selects
129CPU_FAN1 by default, but the user can change that setting if it was built with
130CONFIG_USE_OPTION_TABLE:
131
132```
133$ sudo nvramtool -e cpu_fan_header
134[..]
135$ sudo nvramtool -w cpu_fan_header=CPU_FAN2
136$ sudo nvramtool -w cpu_fan_header=None
137$ sudo nvramtool -w cpu_fan_header=Both
138```
139
140The setting will take effect after a reboot. Selecting and connecting both fan
141headers is possible but the Super I/O will report wrong fan speeds.
142
143Currently there is no automatic, OS-independent fan control, but a software
144like `fancontrol` from the lm-sensors package can be used instead.
145
146## Serial port header
147
148Serial port 1, provided by the Super I/O, is exposed on a pin header. The
149RS-232 signals are assigned to the header so that its pin numbers map directly
150to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
151work, check if your bracket expects a different assignment. Also don't try to
152connect it directly to a device that operates at TTL levels - it would need a
153level converter like a MAX232.
154
155Here is a top view of the serial port header found on this board:
156
157                 +---+---+
158             N/C |   | 9 | RI  -> pin 9
159                 +---+---+
160    Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
161                 +---+---+
162    Pin 6 <- DSR | 6 | 5 | GND -> pin 5
163                 +---+---+
164    Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
165                 +---+---+
166    Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
167                 +---+---+
168
169## eSATA
170
171The eSATA port on the rear I/O panel and the internal connector SATA3_A1 share
172the same controller port on the ASM1061. Attaching an eSATA drive causes a
173multiplexer chip to disconnect the internal port from the SATA controller and
174connect the eSATA port instead. This can be seen on GP23 of the Super I/O
175GPIOs: it is '0' when something is connected to the eSATA port and '1'
176otherwise.
177