xref: /aosp_15_r20/external/clang/test/Sema/arm-special-register.c (revision 67e74705e28f6214e480b399dd47ea732279e315)
1*67e74705SXin Li // RUN: %clang_cc1 -ffreestanding -fsyntax-only -verify -triple arm %s
2*67e74705SXin Li 
string_literal(unsigned v)3*67e74705SXin Li void string_literal(unsigned v) {
4*67e74705SXin Li   __builtin_arm_wsr(0, v); // expected-error {{expression is not a string literal}}
5*67e74705SXin Li }
6*67e74705SXin Li 
wsr_1(unsigned v)7*67e74705SXin Li void wsr_1(unsigned v) {
8*67e74705SXin Li   __builtin_arm_wsr("sysreg", v);
9*67e74705SXin Li }
10*67e74705SXin Li 
wsrp_1(void * v)11*67e74705SXin Li void wsrp_1(void *v) {
12*67e74705SXin Li   __builtin_arm_wsrp("sysreg", v);
13*67e74705SXin Li }
14*67e74705SXin Li 
wsr64_1(unsigned long v)15*67e74705SXin Li void wsr64_1(unsigned long v) {
16*67e74705SXin Li   __builtin_arm_wsr64("sysreg", v); //expected-error {{invalid special register for builtin}}
17*67e74705SXin Li }
18*67e74705SXin Li 
rsr_1()19*67e74705SXin Li unsigned rsr_1() {
20*67e74705SXin Li   return __builtin_arm_rsr("sysreg");
21*67e74705SXin Li }
22*67e74705SXin Li 
rsrp_1()23*67e74705SXin Li void *rsrp_1() {
24*67e74705SXin Li   return __builtin_arm_rsrp("sysreg");
25*67e74705SXin Li }
26*67e74705SXin Li 
rsr64_1()27*67e74705SXin Li unsigned long rsr64_1() {
28*67e74705SXin Li   return __builtin_arm_rsr64("sysreg"); //expected-error {{invalid special register for builtin}}
29*67e74705SXin Li }
30*67e74705SXin Li 
wsr_2(unsigned v)31*67e74705SXin Li void wsr_2(unsigned v) {
32*67e74705SXin Li   __builtin_arm_wsr("cp0:1:c2:c3:4", v);
33*67e74705SXin Li }
34*67e74705SXin Li 
wsrp_2(void * v)35*67e74705SXin Li void wsrp_2(void *v) {
36*67e74705SXin Li   __builtin_arm_wsrp("cp0:1:c2:c3:4", v);
37*67e74705SXin Li }
38*67e74705SXin Li 
wsr64_2(unsigned long v)39*67e74705SXin Li void wsr64_2(unsigned long v) {
40*67e74705SXin Li   __builtin_arm_wsr64("cp0:1:c2:c3:4", v); //expected-error {{invalid special register for builtin}}
41*67e74705SXin Li }
42*67e74705SXin Li 
rsr_2()43*67e74705SXin Li unsigned rsr_2() {
44*67e74705SXin Li   return __builtin_arm_rsr("cp0:1:c2:c3:4");
45*67e74705SXin Li }
46*67e74705SXin Li 
rsrp_2()47*67e74705SXin Li void *rsrp_2() {
48*67e74705SXin Li   return __builtin_arm_rsrp("cp0:1:c2:c3:4");
49*67e74705SXin Li }
50*67e74705SXin Li 
rsr64_2()51*67e74705SXin Li unsigned long rsr64_2() {
52*67e74705SXin Li   return __builtin_arm_rsr64("cp0:1:c2:c3:4"); //expected-error {{invalid special register for builtin}}
53*67e74705SXin Li }
54*67e74705SXin Li 
wsr_3(unsigned v)55*67e74705SXin Li void wsr_3(unsigned v) {
56*67e74705SXin Li   __builtin_arm_wsr("cp0:1:c2", v); //expected-error {{invalid special register for builtin}}
57*67e74705SXin Li }
58*67e74705SXin Li 
wsrp_3(void * v)59*67e74705SXin Li void wsrp_3(void *v) {
60*67e74705SXin Li   __builtin_arm_wsrp("cp0:1:c2", v); //expected-error {{invalid special register for builtin}}
61*67e74705SXin Li }
62*67e74705SXin Li 
wsr64_3(unsigned long v)63*67e74705SXin Li void wsr64_3(unsigned long v) {
64*67e74705SXin Li   __builtin_arm_wsr64("cp0:1:c2", v);
65*67e74705SXin Li }
66*67e74705SXin Li 
rsr_3()67*67e74705SXin Li unsigned rsr_3() {
68*67e74705SXin Li   return __builtin_arm_rsr("cp0:1:c2"); //expected-error {{invalid special register for builtin}}
69*67e74705SXin Li }
70*67e74705SXin Li 
rsrp_3()71*67e74705SXin Li void *rsrp_3() {
72*67e74705SXin Li   return __builtin_arm_rsrp("cp0:1:c2"); //expected-error {{invalid special register for builtin}}
73*67e74705SXin Li }
74*67e74705SXin Li 
rsr64_3()75*67e74705SXin Li unsigned long rsr64_3() {
76*67e74705SXin Li   return __builtin_arm_rsr64("cp0:1:c2");
77*67e74705SXin Li }
78*67e74705SXin Li 
rsr_4()79*67e74705SXin Li unsigned rsr_4() {
80*67e74705SXin Li   return __builtin_arm_rsr("0:1:2:3:4"); //expected-error {{invalid special register for builtin}}
81*67e74705SXin Li }
82*67e74705SXin Li 
rsrp_4()83*67e74705SXin Li void *rsrp_4() {
84*67e74705SXin Li   return __builtin_arm_rsrp("0:1:2:3:4"); //expected-error {{invalid special register for builtin}}
85*67e74705SXin Li }
86*67e74705SXin Li 
rsr64_4()87*67e74705SXin Li unsigned long rsr64_4() {
88*67e74705SXin Li   return __builtin_arm_rsr64("0:1:2"); //expected-error {{invalid special register for builtin}}
89*67e74705SXin Li }
90