1*67e74705SXin Li // RUN: %clang -target mipsel-unknown-linux -S -o - -emit-llvm %s \ 2*67e74705SXin Li // RUN: | FileCheck %s 3*67e74705SXin Li 4*67e74705SXin Li // This checks that the frontend will accept inline asm memory constraints. 5*67e74705SXin Li foo()6*67e74705SXin Liint foo() 7*67e74705SXin Li { 8*67e74705SXin Li 9*67e74705SXin Li // 'R': An address that can be used in a non-macro load or stor' 10*67e74705SXin Li // This test will result in the higher and lower nibbles being 11*67e74705SXin Li // switched due to the lwl/lwr instruction pairs. 12*67e74705SXin Li // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R,~{$1}"(i32* %{{[0-9,a-f]+}}) #1, 13*67e74705SXin Li 14*67e74705SXin Li int c = 0xffbbccdd; 15*67e74705SXin Li 16*67e74705SXin Li int *p = &c; 17*67e74705SXin Li int out = 0; 18*67e74705SXin Li 19*67e74705SXin Li __asm volatile ( 20*67e74705SXin Li "lwl %0, 1 + %1\n\t" 21*67e74705SXin Li "lwr %0, 2 + %1\n\t" 22*67e74705SXin Li : "=r"(out) 23*67e74705SXin Li : "R"(*p) 24*67e74705SXin Li ); 25*67e74705SXin Li return 0; 26*67e74705SXin Li } 27