xref: /aosp_15_r20/external/clang/test/CodeGen/mips-clobber-reg.c (revision 67e74705e28f6214e480b399dd47ea732279e315)
1*67e74705SXin Li // RUN: %clang -target mipsel-unknown-linux -S -o - -emit-llvm %s
2*67e74705SXin Li 
3*67e74705SXin Li /*
4*67e74705SXin Li     This checks that the frontend will accept both
5*67e74705SXin Li     enumerated and symbolic Mips register names.
6*67e74705SXin Li 
7*67e74705SXin Li     Includes:
8*67e74705SXin Li     - GPR
9*67e74705SXin Li     - FPU
10*67e74705SXin Li     - MSA
11*67e74705SXin Li 
12*67e74705SXin Li     Any bad names will make the frontend choke.
13*67e74705SXin Li  */
14*67e74705SXin Li 
main()15*67e74705SXin Li main()
16*67e74705SXin Li {
17*67e74705SXin Li 
18*67e74705SXin Li     __asm__ __volatile__ (".set noat \n\t addi $7,$at,77":::"at");
19*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$v0,77":::"v0");
20*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$v1,77":::"v1");
21*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$a0,77":::"a0");
22*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$a1,77":::"a1");
23*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$a2,77":::"a2");
24*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$a3,77":::"a3");
25*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$t0,77":::"t0");
26*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$t1,77":::"t1");
27*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$t2,77":::"t2");
28*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$t3,77":::"t3");
29*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$t4,77":::"t4");
30*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$t5,77":::"t5");
31*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$t6,77":::"t6");
32*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$t7,77":::"t7");
33*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$s0,77":::"s0");
34*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$s1,77":::"s1");
35*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$s2,77":::"s2");
36*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$s3,77":::"s3");
37*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$s4,77":::"s4");
38*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$s5,77":::"s5");
39*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$s6,77":::"s6");
40*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$s7,77":::"s7");
41*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$t8,77":::"t8");
42*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$t9,77":::"t9");
43*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$k0,77":::"k0");
44*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$k1,77":::"k1");
45*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$gp,77":::"gp");
46*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$sp,77":::"sp");
47*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$fp,77":::"fp");
48*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$sp,77":::"$sp");
49*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$fp,77":::"$fp");
50*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$ra,77":::"ra");
51*67e74705SXin Li 
52*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$0,77":::"$0");
53*67e74705SXin Li     __asm__ __volatile__ (".set noat \n\t addi $7,$1,77":::"$1");
54*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$2,77":::"$2");
55*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$3,77":::"$3");
56*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$4,77":::"$4");
57*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$5,77":::"$5");
58*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$6,77":::"$6");
59*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$7,77":::"$7");
60*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$8,77":::"$8");
61*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$9,77":::"$9");
62*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$10,77":::"$10");
63*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$11,77":::"$11");
64*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$12,77":::"$12");
65*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$13,77":::"$13");
66*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$14,77":::"$14");
67*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$15,77":::"$15");
68*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$16,77":::"$16");
69*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$17,77":::"$17");
70*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$18,77":::"$18");
71*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$19,77":::"$19");
72*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$20,77":::"$20");
73*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$21,77":::"$21");
74*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$22,77":::"$22");
75*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$23,77":::"$23");
76*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$24,77":::"$24");
77*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$25,77":::"$25");
78*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$26,77":::"$26");
79*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$27,77":::"$27");
80*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$28,77":::"$28");
81*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$29,77":::"$29");
82*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$30,77":::"$30");
83*67e74705SXin Li     __asm__ __volatile__ ("addi $7,$31,77":::"$31");
84*67e74705SXin Li 
85*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f0,77":::"$f0");
86*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f1,77":::"$f1");
87*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f2,77":::"$f2");
88*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f3,77":::"$f3");
89*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f4,77":::"$f4");
90*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f5,77":::"$f5");
91*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f6,77":::"$f6");
92*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f7,77":::"$f7");
93*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f8,77":::"$f8");
94*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f9,77":::"$f9");
95*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f10,77":::"$f10");
96*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f11,77":::"$f11");
97*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f12,77":::"$f12");
98*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f13,77":::"$f13");
99*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f14,77":::"$f14");
100*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f15,77":::"$f15");
101*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f16,77":::"$f16");
102*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f17,77":::"$f17");
103*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f18,77":::"$f18");
104*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f19,77":::"$f19");
105*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f20,77":::"$f20");
106*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f21,77":::"$f21");
107*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f22,77":::"$f22");
108*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f23,77":::"$f23");
109*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f24,77":::"$f24");
110*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f25,77":::"$f25");
111*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f26,77":::"$f26");
112*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f27,77":::"$f27");
113*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f28,77":::"$f28");
114*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f29,77":::"$f29");
115*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f30,77":::"$f30");
116*67e74705SXin Li     __asm__ __volatile__ ("fadd.s $f31,77":::"$f31");
117*67e74705SXin Li 
118*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w0,77":::"$w0");
119*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w1,77":::"$w1");
120*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w2,77":::"$w2");
121*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w3,77":::"$w3");
122*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w4,77":::"$w4");
123*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w5,77":::"$w5");
124*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w6,77":::"$w6");
125*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w7,77":::"$w7");
126*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w8,77":::"$w8");
127*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w9,77":::"$w9");
128*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w10,77":::"$w10");
129*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w11,77":::"$w10");
130*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w12,77":::"$w12");
131*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w13,77":::"$w13");
132*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w14,77":::"$w14");
133*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w15,77":::"$w15");
134*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w16,77":::"$w16");
135*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w17,77":::"$w17");
136*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w18,77":::"$w18");
137*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w19,77":::"$w19");
138*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w20,77":::"$w20");
139*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w21,77":::"$w21");
140*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w22,77":::"$w22");
141*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w23,77":::"$w23");
142*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w24,77":::"$w24");
143*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w25,77":::"$w25");
144*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w26,77":::"$w26");
145*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w27,77":::"$w27");
146*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w28,77":::"$w28");
147*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w29,77":::"$w29");
148*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w30,77":::"$w30");
149*67e74705SXin Li     __asm__ __volatile__ ("ldi.w $w31,77":::"$w31");
150*67e74705SXin Li }
151